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Fx2lib
0.2
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Go to the source code of this file.
Defines | |
| #define | INTERRUPT_HIGH_PRIO 1 |
| Interrupt high priority. | |
| #define | INTERRUPT_LOW_PRIO 0 |
| Interrupt low priority. | |
| #define | ENABLE_TIMER0() ET0=1 |
| Enable the timer 0 interrupt. | |
| #define | CLEAR_TIMER0() |
| Clear timer 0 interrupt. | |
| #define | ENABLE_TIMER1() ET1=1 |
| Enable timer 1 interrupt. | |
| #define | CLEAR_TIMER1() |
| Clear timer 1 interrupt. | |
| #define | ENABLE_TIMER2() ET2=1 |
| Enable timer 2 interrupt. | |
| #define | CLEAR_TIMER2() TF2=0;EXF2=0; |
| Clear timer 2 interrupt. | |
| #define | ENABLE_RESUME() ERESI = 1 |
| Enable the Resume Interrupt. Requires EA=1 separately. | |
| #define | CLEAR_RESUME() RESI=0 |
| Clear the resume interrupt. Use within the resume interrupt handler. | |
| #define | ENABLE_INT5() EIEX5=1 |
| Enable external interrupt for INT5#. | |
| #define | CLEAR_INT5() EXIF &= ~bmIE5 |
| Clear INT5# interrupt. | |
| #define | SET_USART0_ISR_PRIORITY(p) PS0 = p |
| Set the USART 0 interrupt priority. | |
| #define | ENABLE_USART0() ES0 = 1; |
| Enable the USART 0 interrupt. | |
| #define | CLEAR_USART0_RX() RI = 0; |
| Clear USART 0 RX bit. | |
| #define | CLEAR_USART0_TX() TI = 0; |
| Clear USART 0 TX bit. | |
| #define | CLEAR_USART0() |
| Clear USART 0 both TX & RX bit. | |
| #define | SET_USART1_ISR_PRIORITY(p) PS1 = p |
| Set the USART 1 interrupt priority. | |
| #define | ENABLE_USART1() ES1 = 1; |
| Enable the USART 1 interrupt. | |
| #define | CLEAR_USART1_RX() RI1 = 0; |
| Clear USART 1 receive (RI1) bit. | |
| #define | CLEAR_USART1_TX() TI1 = 0; |
| Clear USART 1 transmit (TI1) bit. | |
| #define | CLEAR_USART1() |
| Clear USART 1 both TX & RX bits. | |
| #define | SET_I2C_ISR_PRIORITY(p) PI2C = p |
| Set the I2C interrupt priority. | |
| #define | ENABLE_I2C() EI2C = 1; |
| Enable the I2C interrupt. | |
| #define | CLEAR_I2C() EXIF &= ~bmI2CINT; |
| Clear I2C interrupt. | |
Enumerations | |
| enum | FX2_ISR { IE0_ISR = 0, TF0_ISR, IE1_ISR, TF1_ISR, TI_0_ISR, TF2_ISR, RESUME_ISR, TI_1_ISR, USBINT_ISR, I2CINT_ISR, IE4_ISR, IE5_ISR, IE6_ISR, USART0_ISR = TI_0_ISR, USART1_ISR = TI_1_ISR } |
| Interrupt numbers for standard FX2 interrupts. More... | |
Define the standard FX2 interrupts. For INT2 and INT4 autovector interrupts see autovector.h
To enable an interrupt, simply define an interrupt handler function and use the appropriate ENABLE_* macro. Interrupt enable macros do not enable interrupts globally. Use EA=1 to enable interrupts.
void main() { ENABLE_RESUME(); EA=1; ... } void handle_resume() interrupt RESUME_ISR { CLEAR_RESUME(); }
Definition in file fx2ints.h.
| #define CLEAR_INT5 | ( | ) | EXIF &= ~bmIE5 |
| #define CLEAR_RESUME | ( | ) | RESI=0 |
| #define CLEAR_TIMER0 | ( | ) |
Clear timer 0 interrupt.
CLEAR_TIMER0() is a NOP because the timer interrupt flag is automatically cleared when the ISR is called.
| #define CLEAR_TIMER1 | ( | ) |
Clear timer 1 interrupt.
CLEAR_TIMER1() is a NOP because the timer interrupt flag is automatically cleared when the ISR is called.
| #define CLEAR_TIMER2 | ( | ) | TF2=0;EXF2=0; |
| #define CLEAR_USART0 | ( | ) |
CLEAR_USART0_RX(); \ CLEAR_USART0_TX();
Clear USART 0 both TX & RX bit.
| #define CLEAR_USART0_RX | ( | ) | RI = 0; |
| #define CLEAR_USART0_TX | ( | ) | TI = 0; |
| #define CLEAR_USART1 | ( | ) |
CLEAR_USART1_RX(); \ CLEAR_USART1_TX();
Clear USART 1 both TX & RX bits.
| #define CLEAR_USART1_RX | ( | ) | RI1 = 0; |
| #define CLEAR_USART1_TX | ( | ) | TI1 = 0; |
| #define ENABLE_I2C | ( | ) | EI2C = 1; |
| #define ENABLE_INT5 | ( | ) | EIEX5=1 |
| #define ENABLE_RESUME | ( | ) | ERESI = 1 |
| #define ENABLE_TIMER0 | ( | ) | ET0=1 |
Enable the timer 0 interrupt.
CLEAR_TIMER0() is a NOP because the timer interrupt flag is automatically cleared when the ISR is called.
| #define ENABLE_TIMER1 | ( | ) | ET1=1 |
Enable timer 1 interrupt.
CLEAR_TIMER1() is a NOP because the timer interrupt flag is automatically cleared when the ISR is called.
| #define ENABLE_TIMER2 | ( | ) | ET2=1 |
| #define ENABLE_USART0 | ( | ) | ES0 = 1; |
| #define ENABLE_USART1 | ( | ) | ES1 = 1; |
| #define INTERRUPT_HIGH_PRIO 1 |
| #define INTERRUPT_LOW_PRIO 0 |
| #define SET_I2C_ISR_PRIORITY | ( | p | ) | PI2C = p |
Set the I2C interrupt priority.
Does *not* enable the interrupt.
SET_I2C_ISR_PRIO(INTERRUPT_HIGH_PRIO) // Set I2C to high priority SET_I2C_ISR_PRIO(INTERRUPT_LOW_PRIO) // Set I2C to low priority
| #define SET_USART0_ISR_PRIORITY | ( | p | ) | PS0 = p |
Set the USART 0 interrupt priority.
Does *not* enable the interrupt.
SET_USART0_ISR_PRIO(INTERRUPT_HIGH_PRIO); // Set USART0 to high priority SET_USART0_ISR_PRIO(INTERRUPT_LOW_PRIO); // Set USART0 to low priority
| #define SET_USART1_ISR_PRIORITY | ( | p | ) | PS1 = p |
Set the USART 1 interrupt priority.
Does *not* enable the interrupt.
SET_USART1_ISR_PRIO(INTERRUPT_HIGH_PRIO); // Set USART1 to high priority SET_USART1_ISR_PRIO(INTERRUPT_LOW_PRIO); // Set USART1 to low priority
| enum FX2_ISR |
Interrupt numbers for standard FX2 interrupts.
1.7.6.1