#include "fx2types.h"

Defines
#define	EXTAUTODAT1 XAUTODAT1
#define	EXTAUTODAT2 XAUTODAT2
#define	bmPRTCSTB bmBIT5
#define	bmCLKSPD (bmBIT4 \| bmBIT3)
#define	bmCLKSPD1 bmBIT4
#define	bmCLKSPD0 bmBIT3
#define	bmCLKINV bmBIT2
#define	bmCLKOE bmBIT1
#define	bm8051RES bmBIT0
#define	bmFLAGD bmBIT7
#define	bmSLCS bmBIT6
#define	bmINT1 bmBIT1
#define	bmINT0 bmBIT0
#define	bmGPIFA7 bmBIT7
#define	bmGPIFA6 bmBIT6
#define	bmGPIFA5 bmBIT5
#define	bmGPIFA4 bmBIT4
#define	bmGPIFA3 bmBIT3
#define	bmGPIFA2 bmBIT2
#define	bmGPIFA1 bmBIT1
#define	bmGPIFA0 bmBIT0
#define	bmGPIFA8 bmBIT7
#define	bmT2EX bmBIT6
#define	bmINT6 bmBIT5
#define	bmRXD1OUT bmBIT4
#define	bmRXD0OUT bmBIT3
#define	bmT2OUT bmBIT2
#define	bmT1OUT bmBIT1
#define	bmT0OUT bmBIT0
#define	bmSTART bmBIT7
#define	bmSTOP bmBIT6
#define	bmLASTRD bmBIT5
#define	bmID (bmBIT4 \| bmBIT3)
#define	bmBERR bmBIT2
#define	bmACK bmBIT1
#define	bmDONE bmBIT0
#define	bmSTOPIE bmBIT1
#define	bm400KHZ bmBIT0
#define	bmIV4 bmBIT6
#define	bmIV3 bmBIT5
#define	bmIV2 bmBIT4
#define	bmIV1 bmBIT3
#define	bmIV0 bmBIT2
#define	bmEP0ACK bmBIT6
#define	bmHSGRANT bmBIT5
#define	bmURES bmBIT4
#define	bmSUSP bmBIT3
#define	bmSUTOK bmBIT2
#define	bmSOF bmBIT1
#define	bmSUDAV bmBIT0
#define	bmERRLIMIT bmBIT0
#define	bmISOEP2 bmBIT4
#define	bmISOEP4 bmBIT5
#define	bmISOEP6 bmBIT6
#define	bmISOEP8 bmBIT7
#define	bmEP0IN bmBIT0
#define	bmEP0OUT bmBIT1
#define	bmEP1IN bmBIT2
#define	bmEP1OUT bmBIT3
#define	bmEP2 bmBIT4
#define	bmEP4 bmBIT5
#define	bmEP6 bmBIT6
#define	bmEP8 bmBIT7
#define	bmBREAK bmBIT3
#define	bmBPPULSE bmBIT2
#define	bmBPEN bmBIT1
#define	bmAV2EN bmBIT3
#define	INT4IN bmBIT1
#define	bmAV4EN bmBIT0
#define	bmHSM bmBIT7
#define	bmDISCON bmBIT3
#define	bmNOSYNSOF bmBIT2
#define	bmRENUM bmBIT1
#define	bmSIGRESUME bmBIT0
#define	bmWU2 bmBIT7
#define	bmWU bmBIT6
#define	bmWU2POL bmBIT5
#define	bmWUPOL bmBIT4
#define	bmDPEN bmBIT2
#define	bmWU2EN bmBIT1
#define	bmWUEN bmBIT0
#define	bmHSNAK bmBIT7
#define	bmEPBUSY bmBIT1
#define	bmEPSTALL bmBIT0
#define	bmNPAK (bmBIT6 \| bmBIT5 \| bmBIT4)
#define	bmEPFULL bmBIT3
#define	bmEPEMPTY bmBIT2
#define	bmEP8FULL bmBIT7
#define	bmEP8EMPTY bmBIT6
#define	bmEP6FULL bmBIT5
#define	bmEP6EMPTY bmBIT4
#define	bmEP4FULL bmBIT3
#define	bmEP4EMPTY bmBIT2
#define	bmEP2FULL bmBIT1
#define	bmEP2EMPTY bmBIT0
#define	bmVALID bmBIT7
#define	bmDIR bmBIT6
#define	bmTYPE (bmBIT4\|bmBIT5)
#define	bmTYPE1 bmBIT5
#define	bmTYPE0 bmBIT4
#define	bmSIZE bmBIT3
#define	bmBUF (bmBIT0\|bmBIT1)
#define	bmBUF1 bmBIT1
#define	bmBUF0 bmBIT0
#define	bmSDPAUTO bmBIT0
#define	bmQUERYTOGGLE bmBIT7
#define	bmSETTOGGLE bmBIT6
#define	bmRESETTOGGLE bmBIT5
#define	bmTOGCTLEPMASK bmBIT3 \| bmBIT2 \| bmBIT1 \| bmBIT0
#define	bmEP8IBN bmBIT5
#define	bmEP6IBN bmBIT4
#define	bmEP4IBN bmBIT3
#define	bmEP2IBN bmBIT2
#define	bmEP1IBN bmBIT1
#define	bmEP0IBN bmBIT0
#define	bmEP8PING bmBIT7
#define	bmEP6PING bmBIT6
#define	bmEP4PING bmBIT5
#define	bmEP2PING bmBIT4
#define	bmEP1PING bmBIT3
#define	bmEP0PING bmBIT2
#define	bmIBN bmBIT0
#define	bmIFCLKSRC bmBIT7
#define	bm3048MHZ bmBIT6
#define	bmIFCLKOE bmBIT5
#define	bmIFCLKPOL bmBIT4
#define	bmASYNC bmBIT3
#define	bmGSTATE bmBIT2
#define	bmIFCFG1 bmBIT1
#define	bmIFCFG0 bmBIT0
#define	bmIFCFGMASK (bmIFCFG0 \| bmIFCFG1)
#define	bmIFGPIF bmIFCFG1
#define	bmINFM bmBIT6
#define	bmOEP bmBIT5
#define	bmAUTOOUT bmBIT4
#define	bmAUTOIN bmBIT3
#define	bmZEROLENIN bmBIT2
#define	bmWORDWIDE bmBIT0
#define	bmNOAUTOARM bmBIT1
#define	bmSKIPCOMMIT bmBIT0
#define	bmNAKALL bmBIT7
#define	bmFULLSPEEDONLY bmBIT4
#define	bmEP1INBSY bmBIT2
#define	bmEP1OUTBSY bmBIT1
#define	bmEP0BSY bmBIT0
#define	bmIE5 bmBIT7
#define	bmIE4 bmBIT6
#define	bmI2CINT bmBIT5
#define	bmUSBNT bmBIT4
Variables
__xdata __at volatile BYTE	GPIF_WAVE_DATA
__xdata __at volatile BYTE	RES_WAVEDATA_END
__xdata __at volatile BYTE	CPUCS
	Control & Status.
__xdata __at volatile BYTE	IFCONFIG
	Interface Configuration.
__xdata __at volatile BYTE	PINFLAGSAB
	FIFO FLAGA and FLAGB Assignments.
__xdata __at volatile BYTE	PINFLAGSCD
	FIFO FLAGC and FLAGD Assignments.
__xdata __at volatile BYTE	FIFORESET
	Restore FIFOS to default state.
__xdata __at volatile BYTE	BREAKPT
	Breakpoint.
__xdata __at volatile BYTE	BPADDRH
	Breakpoint Address H.
__xdata __at volatile BYTE	BPADDRL
	Breakpoint Address L.
__xdata __at volatile BYTE	UART230
	230 Kbaud clock for T0,T1,T2
__xdata __at volatile BYTE	FIFOPINPOLAR
	FIFO polarities.
__xdata __at volatile BYTE	REVID
	Chip Revision.
__xdata __at volatile BYTE	REVCTL
	Chip Revision Control.
__xdata __at volatile BYTE	EP1OUTCFG
	Endpoint 1-OUT Configuration.
__xdata __at volatile BYTE	EP1INCFG
	Endpoint 1-IN Configuration.
__xdata __at volatile BYTE	EP2CFG
	Endpoint 2 Configuration.
__xdata __at volatile BYTE	EP4CFG
	Endpoint 4 Configuration.
__xdata __at volatile BYTE	EP6CFG
	Endpoint 6 Configuration.
__xdata __at volatile BYTE	EP8CFG
	Endpoint 8 Configuration.
__xdata __at volatile BYTE	EP2FIFOCFG
	Endpoint 2 FIFO configuration.
__xdata __at volatile BYTE	EP4FIFOCFG
	Endpoint 4 FIFO configuration.
__xdata __at volatile BYTE	EP6FIFOCFG
	Endpoint 6 FIFO configuration.
__xdata __at volatile BYTE	EP8FIFOCFG
	Endpoint 8 FIFO configuration.
__xdata __at volatile BYTE	EP2AUTOINLENH
	Endpoint 2 Packet Length H (IN only)
__xdata __at volatile BYTE	EP2AUTOINLENL
	Endpoint 2 Packet Length L (IN only)
__xdata __at volatile BYTE	EP4AUTOINLENH
	Endpoint 4 Packet Length H (IN only)
__xdata __at volatile BYTE	EP4AUTOINLENL
	Endpoint 4 Packet Length L (IN only)
__xdata __at volatile BYTE	EP6AUTOINLENH
	Endpoint 6 Packet Length H (IN only)
__xdata __at volatile BYTE	EP6AUTOINLENL
	Endpoint 6 Packet Length L (IN only)
__xdata __at volatile BYTE	EP8AUTOINLENH
	Endpoint 8 Packet Length H (IN only)
__xdata __at volatile BYTE	EP8AUTOINLENL
	Endpoint 8 Packet Length L (IN only)
__xdata __at volatile BYTE	EP2FIFOPFH
	EP2 Programmable Flag trigger H.
__xdata __at volatile BYTE	EP2FIFOPFL
	EP2 Programmable Flag trigger L.
__xdata __at volatile BYTE	EP4FIFOPFH
	EP4 Programmable Flag trigger H.
__xdata __at volatile BYTE	EP4FIFOPFL
	EP4 Programmable Flag trigger L.
__xdata __at volatile BYTE	EP6FIFOPFH
	EP6 Programmable Flag trigger H.
__xdata __at volatile BYTE	EP6FIFOPFL
	EP6 Programmable Flag trigger L.
__xdata __at volatile BYTE	EP8FIFOPFH
	EP8 Programmable Flag trigger H.
__xdata __at volatile BYTE	EP8FIFOPFL
	EP8 Programmable Flag trigger L.
__xdata __at volatile BYTE	EP2ISOINPKTS
	EP2 (if ISO) IN Packets per frame (1-3)
__xdata __at volatile BYTE	EP4ISOINPKTS
	EP4 (if ISO) IN Packets per frame (1-3)
__xdata __at volatile BYTE	EP6ISOINPKTS
	EP6 (if ISO) IN Packets per frame (1-3)
__xdata __at volatile BYTE	EP8ISOINPKTS
	EP8 (if ISO) IN Packets per frame (1-3)
__xdata __at volatile BYTE	INPKTEND
	Force IN Packet End.
__xdata __at volatile BYTE	OUTPKTEND
	Force OUT Packet End.
__xdata __at volatile BYTE	EP2FIFOIE
	Endpoint 2 Flag Interrupt Enable.
__xdata __at volatile BYTE	EP2FIFOIRQ
	Endpoint 2 Flag Interrupt Request.
__xdata __at volatile BYTE	EP4FIFOIE
	Endpoint 4 Flag Interrupt Enable.
__xdata __at volatile BYTE	EP4FIFOIRQ
	Endpoint 4 Flag Interrupt Request.
__xdata __at volatile BYTE	EP6FIFOIE
	Endpoint 6 Flag Interrupt Enable.
__xdata __at volatile BYTE	EP6FIFOIRQ
	Endpoint 6 Flag Interrupt Request.
__xdata __at volatile BYTE	EP8FIFOIE
	Endpoint 8 Flag Interrupt Enable.
__xdata __at volatile BYTE	EP8FIFOIRQ
	Endpoint 8 Flag Interrupt Request.
__xdata __at volatile BYTE	IBNIE
	IN-BULK-NAK Interrupt Enable.
__xdata __at volatile BYTE	IBNIRQ
	IN-BULK-NAK interrupt Request.
__xdata __at volatile BYTE	NAKIE
	Endpoint Ping NAK interrupt Enable.
__xdata __at volatile BYTE	NAKIRQ
	Endpoint Ping NAK interrupt Request.
__xdata __at volatile BYTE	USBIE
	USB Int Enables.
__xdata __at volatile BYTE	USBIRQ
	USB Interrupt Requests.
__xdata __at volatile BYTE	EPIE
	Endpoint Interrupt Enables.
__xdata __at volatile BYTE	EPIRQ
	Endpoint Interrupt Requests.
__xdata __at volatile BYTE	GPIFIE
	GPIF Interrupt Enable.
__xdata __at volatile BYTE	GPIFIRQ
	GPIF Interrupt Request.
__xdata __at volatile BYTE	USBERRIE
	USB Error Interrupt Enables.
__xdata __at volatile BYTE	USBERRIRQ
	USB Error Interrupt Requests.
__xdata __at volatile BYTE	ERRCNTLIM
	USB Error counter and limit.
__xdata __at volatile BYTE	CLRERRCNT
	Clear Error Counter EC[3..0].
__xdata __at volatile BYTE	INT2IVEC
	Interupt 2 (USB) Autovector.
__xdata __at volatile BYTE	INT4IVEC
	Interupt 4 (FIFOS & GPIF) Autovector.
__xdata __at volatile BYTE	INTSETUP
	Interrupt 2&4 Setup.
__xdata __at volatile BYTE	PORTACFG
	I/O PORTA Alternate Configuration.
__xdata __at volatile BYTE	PORTCCFG
	I/O PORTC Alternate Configuration.
__xdata __at volatile BYTE	PORTECFG
	I/O PORTE Alternate Configuration.
__xdata __at volatile BYTE	I2CS
	Control & Status.
__xdata __at volatile BYTE	I2DAT
	Data.
__xdata __at volatile BYTE	I2CTL
	I2C Control.
__xdata __at volatile BYTE	XAUTODAT1
	Autoptr1 MOVX access.
__xdata __at volatile BYTE	XAUTODAT2
	Autoptr2 MOVX access.
__xdata __at volatile BYTE	USBCS
	USB Control & Status.
__xdata __at volatile BYTE	SUSPEND
	Put chip into suspend.
__xdata __at volatile BYTE	WAKEUPCS
	Wakeup source and polarity.
__xdata __at volatile BYTE	TOGCTL
	Toggle Control.
__xdata __at volatile BYTE	USBFRAMEH
	USB Frame count H.
__xdata __at volatile BYTE	USBFRAMEL
	USB Frame count L.
__xdata __at volatile BYTE	MICROFRAME
	Microframe count, 0-7.
__xdata __at volatile BYTE	FNADDR
	USB Function address.
__xdata __at volatile BYTE	EP0BCH
	Endpoint 0 Byte Count H.
__xdata __at volatile BYTE	EP0BCL
	Endpoint 0 Byte Count L.
__xdata __at volatile BYTE	EP1OUTBC
	Endpoint 1 OUT Byte Count.
__xdata __at volatile BYTE	EP1INBC
	Endpoint 1 IN Byte Count.
__xdata __at volatile BYTE	EP2BCH
	Endpoint 2 Byte Count H.
__xdata __at volatile BYTE	EP2BCL
	Endpoint 2 Byte Count L.
__xdata __at volatile BYTE	EP4BCH
	Endpoint 4 Byte Count H.
__xdata __at volatile BYTE	EP4BCL
	Endpoint 4 Byte Count L.
__xdata __at volatile BYTE	EP6BCH
	Endpoint 6 Byte Count H.
__xdata __at volatile BYTE	EP6BCL
	Endpoint 6 Byte Count L.
__xdata __at volatile BYTE	EP8BCH
	Endpoint 8 Byte Count H.
__xdata __at volatile BYTE	EP8BCL
	Endpoint 8 Byte Count L.
__xdata __at volatile BYTE	EP0CS
	Endpoint Control and Status.
__xdata __at volatile BYTE	EP1OUTCS
	Endpoint 1 OUT Control and Status.
__xdata __at volatile BYTE	EP1INCS
	Endpoint 1 IN Control and Status.
__xdata __at volatile BYTE	EP2CS
	Endpoint 2 Control and Status.
__xdata __at volatile BYTE	EP4CS
	Endpoint 4 Control and Status.
__xdata __at volatile BYTE	EP6CS
	Endpoint 6 Control and Status.
__xdata __at volatile BYTE	EP8CS
	Endpoint 8 Control and Status.
__xdata __at volatile BYTE	EP2FIFOFLGS
	Endpoint 2 Flags.
__xdata __at volatile BYTE	EP4FIFOFLGS
	Endpoint 4 Flags.
__xdata __at volatile BYTE	EP6FIFOFLGS
	Endpoint 6 Flags.
__xdata __at volatile BYTE	EP8FIFOFLGS
	Endpoint 8 Flags.
__xdata __at volatile BYTE	EP2FIFOBCH
	EP2 FIFO total byte count H.
__xdata __at volatile BYTE	EP2FIFOBCL
	EP2 FIFO total byte count L.
__xdata __at volatile BYTE	EP4FIFOBCH
	EP4 FIFO total byte count H.
__xdata __at volatile BYTE	EP4FIFOBCL
	EP4 FIFO total byte count L.
__xdata __at volatile BYTE	EP6FIFOBCH
	EP6 FIFO total byte count H.
__xdata __at volatile BYTE	EP6FIFOBCL
	EP6 FIFO total byte count L.
__xdata __at volatile BYTE	EP8FIFOBCH
	EP8 FIFO total byte count H.
__xdata __at volatile BYTE	EP8FIFOBCL
	EP8 FIFO total byte count L.
__xdata __at volatile BYTE	SUDPTRH
	Setup Data Pointer high address byte.
__xdata __at volatile BYTE	SUDPTRL
	Setup Data Pointer low address byte.
__xdata __at volatile BYTE	SUDPTRCTL
	Setup Data Pointer Auto Mode.
__xdata __at volatile BYTE	SETUPDAT [8]
	8 bytes of SETUP data
__xdata __at volatile BYTE	GPIFWFSELECT
	Waveform Selector.
__xdata __at volatile BYTE	GPIFIDLECS
	GPIF Done, GPIF IDLE drive mode.
__xdata __at volatile BYTE	GPIFIDLECTL
	Inactive Bus, CTL states.
__xdata __at volatile BYTE	GPIFCTLCFG
	CTL OUT pin drive.
__xdata __at volatile BYTE	GPIFADRH
	GPIF Address H.
__xdata __at volatile BYTE	GPIFADRL
	GPIF Address L.
__xdata __at volatile BYTE	GPIFTCB3
	GPIF Transaction Count Byte 3.
__xdata __at volatile BYTE	GPIFTCB2
	GPIF Transaction Count Byte 2.
__xdata __at volatile BYTE	GPIFTCB1
	GPIF Transaction Count Byte 1.
__xdata __at volatile BYTE	GPIFTCB0
	GPIF Transaction Count Byte 0.
__xdata __at volatile BYTE	EP2GPIFFLGSEL
	EP2 GPIF Flag select.
__xdata __at volatile BYTE	EP2GPIFPFSTOP
	Stop GPIF EP2 transaction on prog. flag.
__xdata __at volatile BYTE	EP2GPIFTRIG
	EP2 FIFO Trigger.
__xdata __at volatile BYTE	EP4GPIFFLGSEL
	EP4 GPIF Flag select.
__xdata __at volatile BYTE	EP4GPIFPFSTOP
	Stop GPIF EP4 transaction on prog. flag.
__xdata __at volatile BYTE	EP4GPIFTRIG
	EP4 FIFO Trigger.
__xdata __at volatile BYTE	EP6GPIFFLGSEL
	EP6 GPIF Flag select.
__xdata __at volatile BYTE	EP6GPIFPFSTOP
	Stop GPIF EP6 transaction on prog. flag.
__xdata __at volatile BYTE	EP6GPIFTRIG
	EP6 FIFO Trigger.
__xdata __at volatile BYTE	EP8GPIFFLGSEL
	EP8 GPIF Flag select.
__xdata __at volatile BYTE	EP8GPIFPFSTOP
	Stop GPIF EP8 transaction on prog. flag.
__xdata __at volatile BYTE	EP8GPIFTRIG
	EP8 FIFO Trigger.
__xdata __at volatile BYTE	XGPIFSGLDATH
	GPIF Data H (16-bit mode only)
__xdata __at volatile BYTE	XGPIFSGLDATLX
	Read/Write GPIF Data L & trigger transac.
__xdata __at volatile BYTE	XGPIFSGLDATLNOX
	Read GPIF Data L, no transac trigger.
__xdata __at volatile BYTE	GPIFREADYCFG
	Internal RDY,Sync/Async, RDY5CFG.
__xdata __at volatile BYTE	GPIFREADYSTAT
	RDY pin states.
__xdata __at volatile BYTE	GPIFABORT
	Abort GPIF cycles.
__xdata __at volatile BYTE	FLOWSTATE
	Defines GPIF flow state.
__xdata __at volatile BYTE	FLOWLOGIC
	Defines flow/hold decision criteria.
__xdata __at volatile BYTE	FLOWEQ0CTL
	CTL states during active flow state.
__xdata __at volatile BYTE	FLOWEQ1CTL
	CTL states during hold flow state.
__xdata __at volatile BYTE	FLOWHOLDOFF
__xdata __at volatile BYTE	FLOWSTB
	CTL/RDY Signal to use as master data strobe.
__xdata __at volatile BYTE	FLOWSTBEDGE
	Defines active master strobe edge.
__xdata __at volatile BYTE	FLOWSTBHPERIOD
	Half Period of output master strobe.
__xdata __at volatile BYTE	GPIFHOLDAMOUNT
	Data delay shift.
__xdata __at volatile BYTE	UDMACRCH
	CRC Upper byte.
__xdata __at volatile BYTE	UDMACRCL
	CRC Lower byte.
__xdata __at volatile BYTE	UDMACRCQUAL
	UDMA In only, host terminated use only.
__xdata __at volatile BYTE	EP0BUF [64]
	EP0 IN-OUT buffer.
__xdata __at volatile BYTE	EP1OUTBUF [64]
	EP1-OUT buffer.
__xdata __at volatile BYTE	EP1INBUF [64]
	EP1-IN buffer.
__xdata __at volatile BYTE	EP2FIFOBUF [1024]
	512/1024-byte EP2 buffer (IN or OUT)
__xdata __at volatile BYTE	EP4FIFOBUF [1024]
	512 byte EP4 buffer (IN or OUT)
__xdata __at volatile BYTE	EP6FIFOBUF [1024]
	512/1024-byte EP6 buffer (IN or OUT)
__xdata __at volatile BYTE	EP8FIFOBUF [1024]
	512 byte EP8 buffer (IN or OUT)
__xdata __at volatile BYTE	ECCCFG
	ECC Configuration.
__xdata __at volatile BYTE	ECCRESET
	ECC Reset.
__xdata __at volatile BYTE	ECC1B0
	ECC1 Byte 0.
__xdata __at volatile BYTE	ECC1B1
	ECC1 Byte 1.
__xdata __at volatile BYTE	ECC1B2
	ECC1 Byte 2.
__xdata __at volatile BYTE	ECC2B0
	ECC2 Byte 0.
__xdata __at volatile BYTE	ECC2B1
	ECC2 Byte 1.
__xdata __at volatile BYTE	ECC2B2
	ECC2 Byte 2.
__xdata __at volatile BYTE	GPCR2
	Chip Features.
__sfr __at	IOA
__sbit __at	PA0
__sbit __at	PA1
__sbit __at	PA2
__sbit __at	PA3
__sbit __at	PA4
__sbit __at	PA5
__sbit __at	PA6
__sbit __at	PA7
__sfr __at	SP
__sfr __at	DPL
__sfr __at	DPH
__sfr __at	DPL1
__sfr __at	DPH1
__sfr __at	DPS
__sfr __at	PCON
__sfr __at	TCON
__sbit __at	IT0
__sbit __at	IE0
__sbit __at	IT1
__sbit __at	IE1
__sbit __at	TR0
__sbit __at	TF0
__sbit __at	TR1
__sbit __at	TF1
__sfr __at	TMOD
__sfr __at	TL0
__sfr __at	TL1
__sfr __at	TH0
__sfr __at	TH1
__sfr __at	CKCON
__sfr __at	IOB
__sbit __at	PB0
__sbit __at	PB1
__sbit __at	PB2
__sbit __at	PB3
__sbit __at	PB4
__sbit __at	PB5
__sbit __at	PB6
__sbit __at	PB7
__sfr __at	EXIF
__sfr __at	_XPAGE
__sfr __at	SCON0
__sbit __at	RI
__sbit __at	TI
__sbit __at	RB8
__sbit __at	TB8
__sbit __at	REN
__sbit __at	SM2
__sbit __at	SM1
__sbit __at	SM0
__sfr __at	SBUF0
__sfr __at	AUTOPTRH1
__sfr __at	AUTOPTRL1
__sfr __at	AUTOPTRH2
__sfr __at	AUTOPTRL2
__sfr __at	IOC
__sbit __at	PC0
__sbit __at	PC1
__sbit __at	PC2
__sbit __at	PC3
__sbit __at	PC4
__sbit __at	PC5
__sbit __at	PC6
__sbit __at	PC7
__sfr __at	INT2CLR
__sfr __at	INT4CLR
__sfr __at	IE
__sbit __at	EX0
__sbit __at	ET0
__sbit __at	EX1
__sbit __at	ET1
__sbit __at	ES0
__sbit __at	ET2
__sbit __at	ES1
__sbit __at	EA
__sfr __at	EP2468STAT
__sfr __at	EP24FIFOFLGS
__sfr __at	EP68FIFOFLGS
__sfr __at	AUTOPTRSETUP
__sfr __at	IOD
__sbit __at	PD0
__sbit __at	PD1
__sbit __at	PD2
__sbit __at	PD3
__sbit __at	PD4
__sbit __at	PD5
__sbit __at	PD6
__sbit __at	PD7
__sfr __at	IOE
__sfr __at	OEA
__sfr __at	OEB
__sfr __at	OEC
__sfr __at	OED
__sfr __at	OEE
__sfr __at	IP
__sbit __at	PX0
__sbit __at	PT0
__sbit __at	PX1
__sbit __at	PT1
__sbit __at	PS0
__sbit __at	PT2
__sbit __at	PS1
__sfr __at	EP01STAT
__sfr __at	GPIFTRIG
__sfr __at	GPIFSGLDATH
__sfr __at	GPIFSGLDATLX
__sfr __at	GPIFSGLDATLNOX
__sfr __at	SCON1
__sbit __at	RI1
__sbit __at	TI1
__sbit __at	RB81
__sbit __at	TB81
__sbit __at	REN1
__sbit __at	SM21
__sbit __at	SM11
__sbit __at	SM01
__sfr __at	SBUF1
__sfr __at	T2CON
__sbit __at	CP_RL2
__sbit __at	C_T2
__sbit __at	TR2
__sbit __at	EXEN2
__sbit __at	TCLK
__sbit __at	RCLK
__sbit __at	EXF2
__sbit __at	TF2
__sfr __at	RCAP2L
__sfr __at	RCAP2H
__sfr __at	TL2
__sfr __at	TH2
__sfr __at	PSW
__sbit __at	P
__sbit __at	FL
__sbit __at	OV
__sbit __at	RS0
__sbit __at	RS1
__sbit __at	F0
__sbit __at	AC
__sbit __at	CY
__sfr __at	EICON
__sbit __at	INT6
__sbit __at	RESI
__sbit __at	ERESI
__sbit __at	SMOD1
__sfr __at	ACC
__sfr __at	EIE
__sbit __at	EUSB
__sbit __at	EI2C
__sbit __at	EIEX4
__sbit __at	EIEX5
__sbit __at	EIEX6
__sfr __at	B
__sfr __at	EIP
__sbit __at	PUSB
__sbit __at	PI2C
__sbit __at	EIPX4
__sbit __at	EIPX5
__sbit __at	EIPX6

Detailed Description

This is the basic header/register file for working with the cypress fx2 (cyc768013) and variants 8051 chipset. It contains the special function register definitions as well as the special configuration registers addresses.

The TRM for the fx2 chip contains the full documentation for what each of these registers do.

Definition in file fx2regs.h.

Define Documentation

#define bm3048MHZ bmBIT6

Definition at line 604 of file fx2regs.h.

#define bm400KHZ bmBIT0

Definition at line 496 of file fx2regs.h.

#define bm8051RES bmBIT0

Definition at line 460 of file fx2regs.h.

#define bmACK bmBIT1

Definition at line 492 of file fx2regs.h.

#define bmASYNC bmBIT3

Definition at line 607 of file fx2regs.h.

#define bmAUTOIN bmBIT3

Definition at line 618 of file fx2regs.h.

#define bmAUTOOUT bmBIT4

Definition at line 617 of file fx2regs.h.

#define bmAV2EN bmBIT3

Definition at line 532 of file fx2regs.h.

#define bmAV4EN bmBIT0

Definition at line 534 of file fx2regs.h.

#define bmBERR bmBIT2

Definition at line 491 of file fx2regs.h.

#define bmBPEN bmBIT1

Definition at line 530 of file fx2regs.h.

#define bmBPPULSE bmBIT2

Definition at line 529 of file fx2regs.h.

#define bmBREAK bmBIT3

Definition at line 528 of file fx2regs.h.

#define bmBUF (bmBIT0|bmBIT1)

Definition at line 575 of file fx2regs.h.

#define bmBUF0 bmBIT0

Definition at line 577 of file fx2regs.h.

#define bmBUF1 bmBIT1

Definition at line 576 of file fx2regs.h.

#define bmCLKINV bmBIT2

Definition at line 458 of file fx2regs.h.

#define bmCLKOE bmBIT1

Definition at line 459 of file fx2regs.h.

#define bmCLKSPD (bmBIT4 | bmBIT3)

Definition at line 455 of file fx2regs.h.

#define bmCLKSPD0 bmBIT3

Definition at line 457 of file fx2regs.h.

#define bmCLKSPD1 bmBIT4

Definition at line 456 of file fx2regs.h.

#define bmDIR bmBIT6

Definition at line 569 of file fx2regs.h.

#define bmDISCON bmBIT3

Examples:: fw.c.

Definition at line 537 of file fx2regs.h.

#define bmDONE bmBIT0

Definition at line 493 of file fx2regs.h.

#define bmDPEN bmBIT2

Definition at line 546 of file fx2regs.h.

#define bmEP0ACK bmBIT6

Definition at line 504 of file fx2regs.h.

#define bmEP0BSY bmBIT0

Definition at line 636 of file fx2regs.h.

#define bmEP0IBN bmBIT0

Definition at line 591 of file fx2regs.h.

#define bmEP0IN bmBIT0

Definition at line 519 of file fx2regs.h.

#define bmEP0OUT bmBIT1

Definition at line 520 of file fx2regs.h.

#define bmEP0PING bmBIT2

Definition at line 599 of file fx2regs.h.

#define bmEP1IBN bmBIT1

Definition at line 590 of file fx2regs.h.

#define bmEP1IN bmBIT2

Definition at line 521 of file fx2regs.h.

#define bmEP1INBSY bmBIT2

Definition at line 634 of file fx2regs.h.

#define bmEP1OUT bmBIT3

Definition at line 522 of file fx2regs.h.

#define bmEP1OUTBSY bmBIT1

Definition at line 635 of file fx2regs.h.

#define bmEP1PING bmBIT3

Definition at line 598 of file fx2regs.h.

#define bmEP2 bmBIT4

Definition at line 523 of file fx2regs.h.

#define bmEP2EMPTY bmBIT0

Definition at line 566 of file fx2regs.h.

#define bmEP2FULL bmBIT1

Definition at line 565 of file fx2regs.h.

#define bmEP2IBN bmBIT2

Definition at line 589 of file fx2regs.h.

#define bmEP2PING bmBIT4

Definition at line 597 of file fx2regs.h.

#define bmEP4 bmBIT5

Definition at line 524 of file fx2regs.h.

#define bmEP4EMPTY bmBIT2

Definition at line 564 of file fx2regs.h.

#define bmEP4FULL bmBIT3

Definition at line 563 of file fx2regs.h.

#define bmEP4IBN bmBIT3

Definition at line 588 of file fx2regs.h.

#define bmEP4PING bmBIT5

Definition at line 596 of file fx2regs.h.

#define bmEP6 bmBIT6

Definition at line 525 of file fx2regs.h.

#define bmEP6EMPTY bmBIT4

Definition at line 562 of file fx2regs.h.

#define bmEP6FULL bmBIT5

Definition at line 561 of file fx2regs.h.

#define bmEP6IBN bmBIT4

Definition at line 587 of file fx2regs.h.

#define bmEP6PING bmBIT6

Definition at line 595 of file fx2regs.h.

#define bmEP8 bmBIT7

Definition at line 526 of file fx2regs.h.

#define bmEP8EMPTY bmBIT6

Definition at line 560 of file fx2regs.h.

#define bmEP8FULL bmBIT7

Definition at line 559 of file fx2regs.h.

#define bmEP8IBN bmBIT5

Definition at line 586 of file fx2regs.h.

#define bmEP8PING bmBIT7

Definition at line 594 of file fx2regs.h.

#define bmEPBUSY bmBIT1

Definition at line 552 of file fx2regs.h.

#define bmEPEMPTY bmBIT2

Definition at line 557 of file fx2regs.h.

#define bmEPFULL bmBIT3

Definition at line 556 of file fx2regs.h.

#define bmEPSTALL bmBIT0

Definition at line 553 of file fx2regs.h.

#define bmERRLIMIT bmBIT0

Definition at line 512 of file fx2regs.h.

#define bmFLAGD bmBIT7

Definition at line 463 of file fx2regs.h.

#define bmFULLSPEEDONLY bmBIT4

Definition at line 631 of file fx2regs.h.

#define bmGPIFA0 bmBIT0

Definition at line 475 of file fx2regs.h.

#define bmGPIFA1 bmBIT1

Definition at line 474 of file fx2regs.h.

#define bmGPIFA2 bmBIT2

Definition at line 473 of file fx2regs.h.

#define bmGPIFA3 bmBIT3

Definition at line 472 of file fx2regs.h.

#define bmGPIFA4 bmBIT4

Definition at line 471 of file fx2regs.h.

#define bmGPIFA5 bmBIT5

Definition at line 470 of file fx2regs.h.

#define bmGPIFA6 bmBIT6

Definition at line 469 of file fx2regs.h.

#define bmGPIFA7 bmBIT7

Definition at line 468 of file fx2regs.h.

#define bmGPIFA8 bmBIT7

Definition at line 477 of file fx2regs.h.

#define bmGSTATE bmBIT2

Definition at line 608 of file fx2regs.h.

#define bmHSGRANT bmBIT5

Definition at line 505 of file fx2regs.h.

#define bmHSM bmBIT7

Definition at line 536 of file fx2regs.h.

#define bmHSNAK bmBIT7

Definition at line 550 of file fx2regs.h.

#define bmI2CINT bmBIT5

Definition at line 641 of file fx2regs.h.

#define bmIBN bmBIT0

Definition at line 600 of file fx2regs.h.

#define bmID (bmBIT4 | bmBIT3)

Definition at line 490 of file fx2regs.h.

#define bmIE4 bmBIT6

Definition at line 640 of file fx2regs.h.

#define bmIE5 bmBIT7

Definition at line 639 of file fx2regs.h.

#define bmIFCFG0 bmBIT0

Definition at line 610 of file fx2regs.h.

#define bmIFCFG1 bmBIT1

Definition at line 609 of file fx2regs.h.

#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)

Definition at line 611 of file fx2regs.h.

#define bmIFCLKOE bmBIT5

Definition at line 605 of file fx2regs.h.

#define bmIFCLKPOL bmBIT4

Definition at line 606 of file fx2regs.h.

#define bmIFCLKSRC bmBIT7

Definition at line 603 of file fx2regs.h.

#define bmIFGPIF bmIFCFG1

Definition at line 612 of file fx2regs.h.

#define bmINFM bmBIT6

Definition at line 615 of file fx2regs.h.

#define bmINT0 bmBIT0

Definition at line 466 of file fx2regs.h.

#define bmINT1 bmBIT1

Definition at line 465 of file fx2regs.h.

#define bmINT6 bmBIT5

Definition at line 479 of file fx2regs.h.

#define bmISOEP2 bmBIT4

Definition at line 513 of file fx2regs.h.

#define bmISOEP4 bmBIT5

Definition at line 514 of file fx2regs.h.

#define bmISOEP6 bmBIT6

Definition at line 515 of file fx2regs.h.

#define bmISOEP8 bmBIT7

Definition at line 516 of file fx2regs.h.

#define bmIV0 bmBIT2

Definition at line 502 of file fx2regs.h.

#define bmIV1 bmBIT3

Definition at line 501 of file fx2regs.h.

#define bmIV2 bmBIT4

Definition at line 500 of file fx2regs.h.

#define bmIV3 bmBIT5

Definition at line 499 of file fx2regs.h.

#define bmIV4 bmBIT6

Definition at line 498 of file fx2regs.h.

#define bmLASTRD bmBIT5

Definition at line 489 of file fx2regs.h.

#define bmNAKALL bmBIT7

Definition at line 628 of file fx2regs.h.

#define bmNOAUTOARM bmBIT1

Definition at line 624 of file fx2regs.h.

#define bmNOSYNSOF bmBIT2

Definition at line 538 of file fx2regs.h.

#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)

Definition at line 555 of file fx2regs.h.

#define bmOEP bmBIT5

Definition at line 616 of file fx2regs.h.

#define bmPRTCSTB bmBIT5

Definition at line 454 of file fx2regs.h.

#define bmQUERYTOGGLE bmBIT7

Definition at line 581 of file fx2regs.h.

#define bmRENUM bmBIT1

Definition at line 539 of file fx2regs.h.

#define bmRESETTOGGLE bmBIT5

Definition at line 583 of file fx2regs.h.

#define bmRXD0OUT bmBIT3

Definition at line 481 of file fx2regs.h.

#define bmRXD1OUT bmBIT4

Definition at line 480 of file fx2regs.h.

#define bmSDPAUTO bmBIT0

Definition at line 579 of file fx2regs.h.

#define bmSETTOGGLE bmBIT6

Definition at line 582 of file fx2regs.h.

#define bmSIGRESUME bmBIT0

Examples:: fw.c.

Definition at line 540 of file fx2regs.h.

#define bmSIZE bmBIT3

Definition at line 573 of file fx2regs.h.

#define bmSKIPCOMMIT bmBIT0

Definition at line 625 of file fx2regs.h.

#define bmSLCS bmBIT6

Definition at line 464 of file fx2regs.h.

#define bmSOF bmBIT1

Definition at line 509 of file fx2regs.h.

#define bmSTART bmBIT7

Definition at line 487 of file fx2regs.h.

#define bmSTOP bmBIT6

Definition at line 488 of file fx2regs.h.

#define bmSTOPIE bmBIT1

Definition at line 495 of file fx2regs.h.

#define bmSUDAV bmBIT0

Definition at line 510 of file fx2regs.h.

#define bmSUSP bmBIT3

Definition at line 507 of file fx2regs.h.

#define bmSUTOK bmBIT2

Definition at line 508 of file fx2regs.h.

#define bmT0OUT bmBIT0

Definition at line 484 of file fx2regs.h.

#define bmT1OUT bmBIT1

Definition at line 483 of file fx2regs.h.

#define bmT2EX bmBIT6

Definition at line 478 of file fx2regs.h.

#define bmT2OUT bmBIT2

Definition at line 482 of file fx2regs.h.

#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0

Definition at line 584 of file fx2regs.h.

#define bmTYPE (bmBIT4|bmBIT5)

Definition at line 570 of file fx2regs.h.

#define bmTYPE0 bmBIT4

Definition at line 572 of file fx2regs.h.

#define bmTYPE1 bmBIT5

Definition at line 571 of file fx2regs.h.

#define bmURES bmBIT4

Definition at line 506 of file fx2regs.h.

#define bmUSBNT bmBIT4

Definition at line 642 of file fx2regs.h.

#define bmVALID bmBIT7

Definition at line 568 of file fx2regs.h.

#define bmWORDWIDE bmBIT0

Definition at line 620 of file fx2regs.h.

#define bmWU bmBIT6

Examples:: fw.c.

Definition at line 543 of file fx2regs.h.

#define bmWU2 bmBIT7

Examples:: fw.c.

Definition at line 542 of file fx2regs.h.

#define bmWU2EN bmBIT1

Definition at line 547 of file fx2regs.h.

#define bmWU2POL bmBIT5

Definition at line 544 of file fx2regs.h.

#define bmWUEN bmBIT0

Definition at line 548 of file fx2regs.h.

#define bmWUPOL bmBIT4

Definition at line 545 of file fx2regs.h.

#define bmZEROLENIN bmBIT2

Definition at line 619 of file fx2regs.h.

#define EXTAUTODAT1 XAUTODAT1

Definition at line 135 of file fx2regs.h.

#define EXTAUTODAT2 XAUTODAT2

Definition at line 136 of file fx2regs.h.

#define INT4IN bmBIT1

Definition at line 533 of file fx2regs.h.

Variable Documentation

__sfr __at _XPAGE

Definition at line 314 of file fx2regs.h.

__sbit __at AC

Definition at line 427 of file fx2regs.h.

__sfr __at ACC

Definition at line 435 of file fx2regs.h.

__sfr __at AUTOPTRH1

Definition at line 327 of file fx2regs.h.

__sfr __at AUTOPTRH2

Definition at line 329 of file fx2regs.h.

__sfr __at AUTOPTRL1

Definition at line 328 of file fx2regs.h.

__sfr __at AUTOPTRL2

Definition at line 330 of file fx2regs.h.

__sfr __at AUTOPTRSETUP

Definition at line 359 of file fx2regs.h.

__sfr __at B

Definition at line 443 of file fx2regs.h.

__xdata __at volatile BYTE BPADDRH

Breakpoint Address H.

Definition at line 54 of file fx2regs.h.

__xdata __at volatile BYTE BPADDRL

Breakpoint Address L.

Definition at line 55 of file fx2regs.h.

__xdata __at volatile BYTE BREAKPT

Breakpoint.

Definition at line 53 of file fx2regs.h.

__sbit __at C_T2

Definition at line 408 of file fx2regs.h.

__sfr __at CKCON

Definition at line 300 of file fx2regs.h.

__xdata __at volatile BYTE CLRERRCNT

Clear Error Counter EC[3..0].

Definition at line 119 of file fx2regs.h.

__sbit __at CP_RL2

Definition at line 407 of file fx2regs.h.

__xdata __at volatile BYTE CPUCS

Control & Status.

Definition at line 48 of file fx2regs.h.

__sbit __at CY

Definition at line 428 of file fx2regs.h.

__sfr __at DPH

Definition at line 280 of file fx2regs.h.

__sfr __at DPH1

Definition at line 282 of file fx2regs.h.

__sfr __at DPL

Definition at line 279 of file fx2regs.h.

__sfr __at DPL1

Definition at line 281 of file fx2regs.h.

__sfr __at DPS

Definition at line 283 of file fx2regs.h.

__sbit __at EA

Examples:: fw.c.

Definition at line 354 of file fx2regs.h.

__xdata __at volatile BYTE ECC1B0

ECC1 Byte 0.

Definition at line 249 of file fx2regs.h.

__xdata __at volatile BYTE ECC1B1

ECC1 Byte 1.

Definition at line 250 of file fx2regs.h.

__xdata __at volatile BYTE ECC1B2

ECC1 Byte 2.

Definition at line 251 of file fx2regs.h.

__xdata __at volatile BYTE ECC2B0

ECC2 Byte 0.

Definition at line 252 of file fx2regs.h.

__xdata __at volatile BYTE ECC2B1

ECC2 Byte 1.

Definition at line 253 of file fx2regs.h.

__xdata __at volatile BYTE ECC2B2

ECC2 Byte 2.

Definition at line 254 of file fx2regs.h.

__xdata __at volatile BYTE ECCCFG

ECC Configuration.

Definition at line 247 of file fx2regs.h.

__xdata __at volatile BYTE ECCRESET

ECC Reset.

Definition at line 248 of file fx2regs.h.

__sbit __at EI2C

Definition at line 439 of file fx2regs.h.

__sfr __at EICON

Definition at line 429 of file fx2regs.h.

__sfr __at EIE

Definition at line 436 of file fx2regs.h.

__sbit __at EIEX4

Definition at line 440 of file fx2regs.h.

__sbit __at EIEX5

Definition at line 441 of file fx2regs.h.

__sbit __at EIEX6

Definition at line 442 of file fx2regs.h.

__sfr __at EIP

Definition at line 444 of file fx2regs.h.

__sbit __at EIPX4

Definition at line 448 of file fx2regs.h.

__sbit __at EIPX5

Definition at line 449 of file fx2regs.h.

__sbit __at EIPX6

Definition at line 450 of file fx2regs.h.

__sfr __at EP01STAT

Definition at line 387 of file fx2regs.h.

__xdata __at volatile BYTE EP0BCH

Endpoint 0 Byte Count H.

Definition at line 151 of file fx2regs.h.

__xdata __at volatile BYTE EP0BCL

Endpoint 0 Byte Count L.

Definition at line 152 of file fx2regs.h.

__xdata __at volatile BYTE EP0BUF[64]

EP0 IN-OUT buffer.

Definition at line 237 of file fx2regs.h.

__xdata __at volatile BYTE EP0CS

Endpoint Control and Status.

Definition at line 163 of file fx2regs.h.

__xdata __at volatile BYTE EP1INBC

Endpoint 1 IN Byte Count.

Definition at line 154 of file fx2regs.h.

__xdata __at volatile BYTE EP1INBUF[64]

EP1-IN buffer.

Definition at line 239 of file fx2regs.h.

__xdata __at volatile BYTE EP1INCFG

Endpoint 1-IN Configuration.

Definition at line 64 of file fx2regs.h.

__xdata __at volatile BYTE EP1INCS

Endpoint 1 IN Control and Status.

Definition at line 165 of file fx2regs.h.

__xdata __at volatile BYTE EP1OUTBC

Endpoint 1 OUT Byte Count.

Definition at line 153 of file fx2regs.h.

__xdata __at volatile BYTE EP1OUTBUF[64]

EP1-OUT buffer.

Definition at line 238 of file fx2regs.h.

__xdata __at volatile BYTE EP1OUTCFG

Endpoint 1-OUT Configuration.

Definition at line 63 of file fx2regs.h.

__xdata __at volatile BYTE EP1OUTCS

Endpoint 1 OUT Control and Status.

Definition at line 164 of file fx2regs.h.

__sfr __at EP2468STAT

Definition at line 356 of file fx2regs.h.

__sfr __at EP24FIFOFLGS

Definition at line 357 of file fx2regs.h.

__xdata __at volatile BYTE EP2AUTOINLENH

Endpoint 2 Packet Length H (IN only)

Definition at line 73 of file fx2regs.h.

__xdata __at volatile BYTE EP2AUTOINLENL

Endpoint 2 Packet Length L (IN only)

Definition at line 74 of file fx2regs.h.

__xdata __at volatile BYTE EP2BCH

Endpoint 2 Byte Count H.

Definition at line 155 of file fx2regs.h.

__xdata __at volatile BYTE EP2BCL

Endpoint 2 Byte Count L.

Definition at line 156 of file fx2regs.h.

__xdata __at volatile BYTE EP2CFG

Endpoint 2 Configuration.

Definition at line 65 of file fx2regs.h.

__xdata __at volatile BYTE EP2CS

Endpoint 2 Control and Status.

Definition at line 166 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOBCH

EP2 FIFO total byte count H.

Definition at line 174 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOBCL

EP2 FIFO total byte count L.

Definition at line 175 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOBUF[1024]

512/1024-byte EP2 buffer (IN or OUT)

Definition at line 240 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOCFG

Endpoint 2 FIFO configuration.

Definition at line 69 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOFLGS

Endpoint 2 Flags.

Definition at line 170 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOIE

Endpoint 2 Flag Interrupt Enable.

Definition at line 98 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOIRQ

Endpoint 2 Flag Interrupt Request.

Definition at line 99 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOPFH

EP2 Programmable Flag trigger H.

Definition at line 81 of file fx2regs.h.

__xdata __at volatile BYTE EP2FIFOPFL

EP2 Programmable Flag trigger L.

Definition at line 82 of file fx2regs.h.

__xdata __at volatile BYTE EP2GPIFFLGSEL

EP2 GPIF Flag select.

Definition at line 201 of file fx2regs.h.

__xdata __at volatile BYTE EP2GPIFPFSTOP

Stop GPIF EP2 transaction on prog. flag.

Definition at line 202 of file fx2regs.h.

__xdata __at volatile BYTE EP2GPIFTRIG

EP2 FIFO Trigger.

Definition at line 203 of file fx2regs.h.

__xdata __at volatile BYTE EP2ISOINPKTS

EP2 (if ISO) IN Packets per frame (1-3)

Definition at line 89 of file fx2regs.h.

__xdata __at volatile BYTE EP4AUTOINLENH

Endpoint 4 Packet Length H (IN only)

Definition at line 75 of file fx2regs.h.

__xdata __at volatile BYTE EP4AUTOINLENL

Endpoint 4 Packet Length L (IN only)

Definition at line 76 of file fx2regs.h.

__xdata __at volatile BYTE EP4BCH

Endpoint 4 Byte Count H.

Definition at line 157 of file fx2regs.h.

__xdata __at volatile BYTE EP4BCL

Endpoint 4 Byte Count L.

Definition at line 158 of file fx2regs.h.

__xdata __at volatile BYTE EP4CFG

Endpoint 4 Configuration.

Definition at line 66 of file fx2regs.h.

__xdata __at volatile BYTE EP4CS

Endpoint 4 Control and Status.

Definition at line 167 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOBCH

EP4 FIFO total byte count H.

Definition at line 176 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOBCL

EP4 FIFO total byte count L.

Definition at line 177 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOBUF[1024]

512 byte EP4 buffer (IN or OUT)

Definition at line 241 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOCFG

Endpoint 4 FIFO configuration.

Definition at line 70 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOFLGS

Endpoint 4 Flags.

Definition at line 171 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOIE

Endpoint 4 Flag Interrupt Enable.

Definition at line 100 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOIRQ

Endpoint 4 Flag Interrupt Request.

Definition at line 101 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOPFH

EP4 Programmable Flag trigger H.

Definition at line 83 of file fx2regs.h.

__xdata __at volatile BYTE EP4FIFOPFL

EP4 Programmable Flag trigger L.

Definition at line 84 of file fx2regs.h.

__xdata __at volatile BYTE EP4GPIFFLGSEL

EP4 GPIF Flag select.

Definition at line 204 of file fx2regs.h.

__xdata __at volatile BYTE EP4GPIFPFSTOP

Stop GPIF EP4 transaction on prog. flag.

Definition at line 205 of file fx2regs.h.

__xdata __at volatile BYTE EP4GPIFTRIG

EP4 FIFO Trigger.

Definition at line 206 of file fx2regs.h.

__xdata __at volatile BYTE EP4ISOINPKTS

EP4 (if ISO) IN Packets per frame (1-3)

Definition at line 90 of file fx2regs.h.

__sfr __at EP68FIFOFLGS

Definition at line 358 of file fx2regs.h.

__xdata __at volatile BYTE EP6AUTOINLENH

Endpoint 6 Packet Length H (IN only)

Definition at line 77 of file fx2regs.h.

__xdata __at volatile BYTE EP6AUTOINLENL

Endpoint 6 Packet Length L (IN only)

Definition at line 78 of file fx2regs.h.

__xdata __at volatile BYTE EP6BCH

Endpoint 6 Byte Count H.

Definition at line 159 of file fx2regs.h.

__xdata __at volatile BYTE EP6BCL

Endpoint 6 Byte Count L.

Definition at line 160 of file fx2regs.h.

__xdata __at volatile BYTE EP6CFG

Endpoint 6 Configuration.

Definition at line 67 of file fx2regs.h.

__xdata __at volatile BYTE EP6CS

Endpoint 6 Control and Status.

Definition at line 168 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOBCH

EP6 FIFO total byte count H.

Definition at line 178 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOBCL

EP6 FIFO total byte count L.

Definition at line 179 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOBUF[1024]

512/1024-byte EP6 buffer (IN or OUT)

Definition at line 242 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOCFG

Endpoint 6 FIFO configuration.

Definition at line 71 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOFLGS

Endpoint 6 Flags.

Definition at line 172 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOIE

Endpoint 6 Flag Interrupt Enable.

Definition at line 102 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOIRQ

Endpoint 6 Flag Interrupt Request.

Definition at line 103 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOPFH

EP6 Programmable Flag trigger H.

Definition at line 85 of file fx2regs.h.

__xdata __at volatile BYTE EP6FIFOPFL

EP6 Programmable Flag trigger L.

Definition at line 86 of file fx2regs.h.

__xdata __at volatile BYTE EP6GPIFFLGSEL

EP6 GPIF Flag select.

Definition at line 207 of file fx2regs.h.

__xdata __at volatile BYTE EP6GPIFPFSTOP

Stop GPIF EP6 transaction on prog. flag.

Definition at line 208 of file fx2regs.h.

__xdata __at volatile BYTE EP6GPIFTRIG

EP6 FIFO Trigger.

Definition at line 209 of file fx2regs.h.

__xdata __at volatile BYTE EP6ISOINPKTS

EP6 (if ISO) IN Packets per frame (1-3)

Definition at line 91 of file fx2regs.h.

__xdata __at volatile BYTE EP8AUTOINLENH

Endpoint 8 Packet Length H (IN only)

Definition at line 79 of file fx2regs.h.

__xdata __at volatile BYTE EP8AUTOINLENL

Endpoint 8 Packet Length L (IN only)

Definition at line 80 of file fx2regs.h.

__xdata __at volatile BYTE EP8BCH

Endpoint 8 Byte Count H.

Definition at line 161 of file fx2regs.h.

__xdata __at volatile BYTE EP8BCL

Endpoint 8 Byte Count L.

Definition at line 162 of file fx2regs.h.

__xdata __at volatile BYTE EP8CFG

Endpoint 8 Configuration.

Definition at line 68 of file fx2regs.h.

__xdata __at volatile BYTE EP8CS

Endpoint 8 Control and Status.

Definition at line 169 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOBCH

EP8 FIFO total byte count H.

Definition at line 180 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOBCL

EP8 FIFO total byte count L.

Definition at line 181 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOBUF[1024]

512 byte EP8 buffer (IN or OUT)

Definition at line 243 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOCFG

Endpoint 8 FIFO configuration.

Definition at line 72 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOFLGS

Endpoint 8 Flags.

Definition at line 173 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOIE

Endpoint 8 Flag Interrupt Enable.

Definition at line 104 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOIRQ

Endpoint 8 Flag Interrupt Request.

Definition at line 105 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOPFH

EP8 Programmable Flag trigger H.

Definition at line 87 of file fx2regs.h.

__xdata __at volatile BYTE EP8FIFOPFL

EP8 Programmable Flag trigger L.

Definition at line 88 of file fx2regs.h.

__xdata __at volatile BYTE EP8GPIFFLGSEL

EP8 GPIF Flag select.

Definition at line 210 of file fx2regs.h.

__xdata __at volatile BYTE EP8GPIFPFSTOP

Stop GPIF EP8 transaction on prog. flag.

Definition at line 211 of file fx2regs.h.

__xdata __at volatile BYTE EP8GPIFTRIG

EP8 FIFO Trigger.

Definition at line 212 of file fx2regs.h.

__xdata __at volatile BYTE EP8ISOINPKTS

EP8 (if ISO) IN Packets per frame (1-3)

Definition at line 92 of file fx2regs.h.

__xdata __at volatile BYTE EPIE

Endpoint Interrupt Enables.

Definition at line 112 of file fx2regs.h.

__xdata __at volatile BYTE EPIRQ

Endpoint Interrupt Requests.

Definition at line 113 of file fx2regs.h.

__sbit __at ERESI

Definition at line 433 of file fx2regs.h.

__xdata __at volatile BYTE ERRCNTLIM

USB Error counter and limit.

Definition at line 118 of file fx2regs.h.

__sbit __at ES0

Definition at line 351 of file fx2regs.h.

__sbit __at ES1

Definition at line 353 of file fx2regs.h.

__sbit __at ET0

Definition at line 348 of file fx2regs.h.

__sbit __at ET1

Definition at line 350 of file fx2regs.h.

__sbit __at ET2

Definition at line 352 of file fx2regs.h.

__sbit __at EUSB

Definition at line 438 of file fx2regs.h.

__sbit __at EX0

Definition at line 347 of file fx2regs.h.

__sbit __at EX1

Definition at line 349 of file fx2regs.h.

__sbit __at EXEN2

Definition at line 410 of file fx2regs.h.

__sbit __at EXF2

Definition at line 413 of file fx2regs.h.

__sfr __at EXIF

Definition at line 311 of file fx2regs.h.

__sbit __at F0

Definition at line 426 of file fx2regs.h.

__xdata __at volatile BYTE FIFOPINPOLAR

FIFO polarities.

Definition at line 57 of file fx2regs.h.

__xdata __at volatile BYTE FIFORESET

Restore FIFOS to default state.

Definition at line 52 of file fx2regs.h.

__sbit __at FL

Definition at line 422 of file fx2regs.h.

__xdata __at volatile BYTE FLOWEQ0CTL

CTL states during active flow state.

Definition at line 224 of file fx2regs.h.

__xdata __at volatile BYTE FLOWEQ1CTL

CTL states during hold flow state.

Definition at line 225 of file fx2regs.h.

__xdata __at volatile BYTE FLOWHOLDOFF

Definition at line 226 of file fx2regs.h.

__xdata __at volatile BYTE FLOWLOGIC

Defines flow/hold decision criteria.

Definition at line 223 of file fx2regs.h.

__xdata __at volatile BYTE FLOWSTATE

Defines GPIF flow state.

Definition at line 222 of file fx2regs.h.

__xdata __at volatile BYTE FLOWSTB

CTL/RDY Signal to use as master data strobe.

Definition at line 227 of file fx2regs.h.

__xdata __at volatile BYTE FLOWSTBEDGE

Defines active master strobe edge.

Definition at line 228 of file fx2regs.h.

__xdata __at volatile BYTE FLOWSTBHPERIOD

Half Period of output master strobe.

Definition at line 229 of file fx2regs.h.

__xdata __at volatile BYTE FNADDR

USB Function address.

Definition at line 147 of file fx2regs.h.

__xdata __at volatile BYTE GPCR2

Chip Features.

Definition at line 257 of file fx2regs.h.

__xdata __at volatile BYTE GPIF_WAVE_DATA

Definition at line 43 of file fx2regs.h.

__xdata __at volatile BYTE GPIFABORT

Abort GPIF cycles.

Definition at line 218 of file fx2regs.h.

__xdata __at volatile BYTE GPIFADRH

GPIF Address H.

Definition at line 193 of file fx2regs.h.

__xdata __at volatile BYTE GPIFADRL

GPIF Address L.

Definition at line 194 of file fx2regs.h.

__xdata __at volatile BYTE GPIFCTLCFG

CTL OUT pin drive.

Definition at line 192 of file fx2regs.h.

__xdata __at volatile BYTE GPIFHOLDAMOUNT

Data delay shift.

Definition at line 230 of file fx2regs.h.

__xdata __at volatile BYTE GPIFIDLECS

GPIF Done, GPIF IDLE drive mode.

Definition at line 190 of file fx2regs.h.

__xdata __at volatile BYTE GPIFIDLECTL

Inactive Bus, CTL states.

Definition at line 191 of file fx2regs.h.

__xdata __at volatile BYTE GPIFIE

GPIF Interrupt Enable.

Definition at line 114 of file fx2regs.h.

__xdata __at volatile BYTE GPIFIRQ

GPIF Interrupt Request.

Definition at line 115 of file fx2regs.h.

__xdata __at volatile BYTE GPIFREADYCFG

Internal RDY,Sync/Async, RDY5CFG.

Definition at line 216 of file fx2regs.h.

__xdata __at volatile BYTE GPIFREADYSTAT

RDY pin states.

Definition at line 217 of file fx2regs.h.

__sfr __at GPIFSGLDATH

Definition at line 390 of file fx2regs.h.

__sfr __at GPIFSGLDATLNOX

Definition at line 392 of file fx2regs.h.

__sfr __at GPIFSGLDATLX

Definition at line 391 of file fx2regs.h.

__xdata __at volatile BYTE GPIFTCB0

GPIF Transaction Count Byte 0.

Definition at line 199 of file fx2regs.h.

__xdata __at volatile BYTE GPIFTCB1

GPIF Transaction Count Byte 1.

Definition at line 198 of file fx2regs.h.

__xdata __at volatile BYTE GPIFTCB2

GPIF Transaction Count Byte 2.

Definition at line 197 of file fx2regs.h.

__xdata __at volatile BYTE GPIFTCB3

GPIF Transaction Count Byte 3.

Definition at line 196 of file fx2regs.h.

__sfr __at GPIFTRIG

Definition at line 388 of file fx2regs.h.

__xdata __at volatile BYTE GPIFWFSELECT

Waveform Selector.

Definition at line 189 of file fx2regs.h.

__xdata __at volatile BYTE I2CS

Control & Status.

Definition at line 129 of file fx2regs.h.

__xdata __at volatile BYTE I2CTL

I2C Control.

Definition at line 131 of file fx2regs.h.

__xdata __at volatile BYTE I2DAT

Data.

Definition at line 130 of file fx2regs.h.

__xdata __at volatile BYTE IBNIE

IN-BULK-NAK Interrupt Enable.

Definition at line 106 of file fx2regs.h.

__xdata __at volatile BYTE IBNIRQ

IN-BULK-NAK interrupt Request.

Definition at line 107 of file fx2regs.h.

__sfr __at IE

Definition at line 345 of file fx2regs.h.

__sbit __at IE0

Definition at line 288 of file fx2regs.h.

__sbit __at IE1

Definition at line 290 of file fx2regs.h.

__xdata __at volatile BYTE IFCONFIG

Interface Configuration.

Definition at line 49 of file fx2regs.h.

__xdata __at volatile BYTE INPKTEND

Force IN Packet End.

Definition at line 93 of file fx2regs.h.

__sfr __at INT2CLR

Definition at line 342 of file fx2regs.h.

__xdata __at volatile BYTE INT2IVEC

Interupt 2 (USB) Autovector.

Definition at line 120 of file fx2regs.h.

__sfr __at INT4CLR

Definition at line 343 of file fx2regs.h.

__xdata __at volatile BYTE INT4IVEC

Interupt 4 (FIFOS & GPIF) Autovector.

Definition at line 121 of file fx2regs.h.

__sbit __at INT6

Definition at line 431 of file fx2regs.h.

__xdata __at volatile BYTE INTSETUP

Interrupt 2&4 Setup.

Definition at line 122 of file fx2regs.h.

__sfr __at IOA

SFRs below According to TRM 15.2, only rows 0 and 8 of the SFRs are bit addressible row 0: IOA, IOB, IOC, IOD, SCON1, PSW, ACC, B row 8: TCON, SCON0, IE, IP, T2CON, IECON, EIE, EIP

All others have to move a byte to the SRF address

Definition at line 268 of file fx2regs.h.

__sfr __at IOB

Definition at line 301 of file fx2regs.h.

__sfr __at IOC

Definition at line 332 of file fx2regs.h.

__sfr __at IOD

Definition at line 360 of file fx2regs.h.

__sfr __at IOE

Definition at line 370 of file fx2regs.h.

__sfr __at IP

Definition at line 377 of file fx2regs.h.

__sbit __at IT0

Definition at line 287 of file fx2regs.h.

__sbit __at IT1

Definition at line 289 of file fx2regs.h.

__xdata __at volatile BYTE MICROFRAME

Microframe count, 0-7.

Definition at line 146 of file fx2regs.h.

__xdata __at volatile BYTE NAKIE

Endpoint Ping NAK interrupt Enable.

Definition at line 108 of file fx2regs.h.

__xdata __at volatile BYTE NAKIRQ

Endpoint Ping NAK interrupt Request.

Definition at line 109 of file fx2regs.h.

__sfr __at OEA

Definition at line 371 of file fx2regs.h.

__sfr __at OEB

Definition at line 372 of file fx2regs.h.

__sfr __at OEC

Definition at line 373 of file fx2regs.h.

__sfr __at OED

Definition at line 374 of file fx2regs.h.

__sfr __at OEE

Definition at line 375 of file fx2regs.h.

__xdata __at volatile BYTE OUTPKTEND

Force OUT Packet End.

Definition at line 94 of file fx2regs.h.

__sbit __at OV

Definition at line 423 of file fx2regs.h.

__sbit __at P

Definition at line 421 of file fx2regs.h.

__sbit __at PA0

Definition at line 270 of file fx2regs.h.

__sbit __at PA1

Definition at line 271 of file fx2regs.h.

__sbit __at PA2

Definition at line 272 of file fx2regs.h.

__sbit __at PA3

Definition at line 273 of file fx2regs.h.

__sbit __at PA4

Definition at line 274 of file fx2regs.h.

__sbit __at PA5

Definition at line 275 of file fx2regs.h.

__sbit __at PA6

Definition at line 276 of file fx2regs.h.

__sbit __at PA7

Definition at line 277 of file fx2regs.h.

__sbit __at PB0

Definition at line 303 of file fx2regs.h.

__sbit __at PB1

Definition at line 304 of file fx2regs.h.

__sbit __at PB2

Definition at line 305 of file fx2regs.h.

__sbit __at PB3

Definition at line 306 of file fx2regs.h.

__sbit __at PB4

Definition at line 307 of file fx2regs.h.

__sbit __at PB5

Definition at line 308 of file fx2regs.h.

__sbit __at PB6

Definition at line 309 of file fx2regs.h.

__sbit __at PB7

Definition at line 310 of file fx2regs.h.

__sbit __at PC0

Definition at line 334 of file fx2regs.h.

__sbit __at PC1

Definition at line 335 of file fx2regs.h.

__sbit __at PC2

Definition at line 336 of file fx2regs.h.

__sbit __at PC3

Definition at line 337 of file fx2regs.h.

__sbit __at PC4

Definition at line 338 of file fx2regs.h.

__sbit __at PC5

Definition at line 339 of file fx2regs.h.

__sbit __at PC6

Definition at line 340 of file fx2regs.h.

__sbit __at PC7

Definition at line 341 of file fx2regs.h.

__sfr __at PCON

Examples:: fw.c.

Definition at line 284 of file fx2regs.h.

__sbit __at PD0

Definition at line 362 of file fx2regs.h.

__sbit __at PD1

Definition at line 363 of file fx2regs.h.

__sbit __at PD2

Definition at line 364 of file fx2regs.h.

__sbit __at PD3

Definition at line 365 of file fx2regs.h.

__sbit __at PD4

Definition at line 366 of file fx2regs.h.

__sbit __at PD5

Definition at line 367 of file fx2regs.h.

__sbit __at PD6

Definition at line 368 of file fx2regs.h.

__sbit __at PD7

Definition at line 369 of file fx2regs.h.

__sbit __at PI2C

Definition at line 447 of file fx2regs.h.

__xdata __at volatile BYTE PINFLAGSAB

FIFO FLAGA and FLAGB Assignments.

Definition at line 50 of file fx2regs.h.

__xdata __at volatile BYTE PINFLAGSCD

FIFO FLAGC and FLAGD Assignments.

Definition at line 51 of file fx2regs.h.

__xdata __at volatile BYTE PORTACFG

I/O PORTA Alternate Configuration.

Definition at line 126 of file fx2regs.h.

__xdata __at volatile BYTE PORTCCFG

I/O PORTC Alternate Configuration.

Definition at line 127 of file fx2regs.h.

__xdata __at volatile BYTE PORTECFG

I/O PORTE Alternate Configuration.

Definition at line 128 of file fx2regs.h.

__sbit __at PS0

Definition at line 383 of file fx2regs.h.

__sbit __at PS1

Definition at line 385 of file fx2regs.h.

__sfr __at PSW

Definition at line 419 of file fx2regs.h.

__sbit __at PT0

Definition at line 380 of file fx2regs.h.

__sbit __at PT1

Definition at line 382 of file fx2regs.h.

__sbit __at PT2

Definition at line 384 of file fx2regs.h.

__sbit __at PUSB

Definition at line 446 of file fx2regs.h.

__sbit __at PX0

Definition at line 379 of file fx2regs.h.

__sbit __at PX1

Definition at line 381 of file fx2regs.h.

__sbit __at RB8

Definition at line 319 of file fx2regs.h.

__sbit __at RB81

Definition at line 398 of file fx2regs.h.

__sfr __at RCAP2H

Definition at line 416 of file fx2regs.h.

__sfr __at RCAP2L

Definition at line 415 of file fx2regs.h.

__sbit __at RCLK

Definition at line 412 of file fx2regs.h.

__sbit __at REN

Definition at line 321 of file fx2regs.h.

__sbit __at REN1

Definition at line 400 of file fx2regs.h.

__xdata __at volatile BYTE RES_WAVEDATA_END

Definition at line 44 of file fx2regs.h.

__sbit __at RESI

Definition at line 432 of file fx2regs.h.

__xdata __at volatile BYTE REVCTL

Chip Revision Control.

Definition at line 59 of file fx2regs.h.

__xdata __at volatile BYTE REVID

Chip Revision.

Definition at line 58 of file fx2regs.h.

__sbit __at RI

Definition at line 317 of file fx2regs.h.

__sbit __at RI1

Definition at line 396 of file fx2regs.h.

__sbit __at RS0

Definition at line 424 of file fx2regs.h.

__sbit __at RS1

Definition at line 425 of file fx2regs.h.

__sfr __at SBUF0

Definition at line 325 of file fx2regs.h.

__sfr __at SBUF1

Definition at line 404 of file fx2regs.h.

__sfr __at SCON0

Definition at line 315 of file fx2regs.h.

__sfr __at SCON1

Definition at line 394 of file fx2regs.h.

__xdata __at volatile BYTE SETUPDAT[8]

8 bytes of SETUP data

Definition at line 185 of file fx2regs.h.

__sbit __at SM0

Definition at line 324 of file fx2regs.h.

__sbit __at SM01

Definition at line 403 of file fx2regs.h.

__sbit __at SM1

Definition at line 323 of file fx2regs.h.

__sbit __at SM11

Definition at line 402 of file fx2regs.h.

__sbit __at SM2

Definition at line 322 of file fx2regs.h.

__sbit __at SM21

Definition at line 401 of file fx2regs.h.

__sbit __at SMOD1

Definition at line 434 of file fx2regs.h.

__sfr __at SP

Definition at line 278 of file fx2regs.h.

__xdata __at volatile BYTE SUDPTRCTL

Setup Data Pointer Auto Mode.

Definition at line 184 of file fx2regs.h.

__xdata __at volatile BYTE SUDPTRH

Setup Data Pointer high address byte.

Definition at line 182 of file fx2regs.h.

__xdata __at volatile BYTE SUDPTRL

Setup Data Pointer low address byte.

Definition at line 183 of file fx2regs.h.

__xdata __at volatile BYTE SUSPEND

Put chip into suspend.

Examples:: fw.c.

Definition at line 141 of file fx2regs.h.

__sfr __at T2CON

Definition at line 405 of file fx2regs.h.

__sbit __at TB8

Definition at line 320 of file fx2regs.h.

__sbit __at TB81

Definition at line 399 of file fx2regs.h.

__sbit __at TCLK

Definition at line 411 of file fx2regs.h.

__sfr __at TCON

Definition at line 285 of file fx2regs.h.

__sbit __at TF0

Definition at line 292 of file fx2regs.h.

__sbit __at TF1

Definition at line 294 of file fx2regs.h.

__sbit __at TF2

Definition at line 414 of file fx2regs.h.

__sfr __at TH0

Definition at line 298 of file fx2regs.h.

__sfr __at TH1

Definition at line 299 of file fx2regs.h.

__sfr __at TH2

Definition at line 418 of file fx2regs.h.

__sbit __at TI

Definition at line 318 of file fx2regs.h.

__sbit __at TI1

Definition at line 397 of file fx2regs.h.

__sfr __at TL0

Definition at line 296 of file fx2regs.h.

__sfr __at TL1

Definition at line 297 of file fx2regs.h.

__sfr __at TL2

Definition at line 417 of file fx2regs.h.

__sfr __at TMOD

Definition at line 295 of file fx2regs.h.

__xdata __at volatile BYTE TOGCTL

Toggle Control.

Definition at line 143 of file fx2regs.h.

__sbit __at TR0

Definition at line 291 of file fx2regs.h.

__sbit __at TR1

Definition at line 293 of file fx2regs.h.

__sbit __at TR2

Definition at line 409 of file fx2regs.h.

__xdata __at volatile BYTE UART230

230 Kbaud clock for T0,T1,T2

Definition at line 56 of file fx2regs.h.

__xdata __at volatile BYTE UDMACRCH

CRC Upper byte.

Definition at line 231 of file fx2regs.h.

__xdata __at volatile BYTE UDMACRCL

CRC Lower byte.

Definition at line 232 of file fx2regs.h.

__xdata __at volatile BYTE UDMACRCQUAL

UDMA In only, host terminated use only.

Definition at line 233 of file fx2regs.h.

__xdata __at volatile BYTE USBCS

USB Control & Status.

Examples:: fw.c.

Definition at line 140 of file fx2regs.h.

__xdata __at volatile BYTE USBERRIE

USB Error Interrupt Enables.

Definition at line 116 of file fx2regs.h.

__xdata __at volatile BYTE USBERRIRQ

USB Error Interrupt Requests.

Definition at line 117 of file fx2regs.h.

__xdata __at volatile BYTE USBFRAMEH

USB Frame count H.

Definition at line 144 of file fx2regs.h.

__xdata __at volatile BYTE USBFRAMEL

USB Frame count L.

Definition at line 145 of file fx2regs.h.

__xdata __at volatile BYTE USBIE

USB Int Enables.

Definition at line 110 of file fx2regs.h.

__xdata __at volatile BYTE USBIRQ

USB Interrupt Requests.

Definition at line 111 of file fx2regs.h.

__xdata __at volatile BYTE WAKEUPCS

Wakeup source and polarity.

Examples:: fw.c.

Definition at line 142 of file fx2regs.h.

__xdata __at volatile BYTE XAUTODAT1

Autoptr1 MOVX access.

Definition at line 132 of file fx2regs.h.

__xdata __at volatile BYTE XAUTODAT2

Autoptr2 MOVX access.

Definition at line 133 of file fx2regs.h.

__xdata __at volatile BYTE XGPIFSGLDATH

GPIF Data H (16-bit mode only)

Definition at line 213 of file fx2regs.h.

__xdata __at volatile BYTE XGPIFSGLDATLNOX

Read GPIF Data L, no transac trigger.

Definition at line 215 of file fx2regs.h.

__xdata __at volatile BYTE XGPIFSGLDATLX

Read/Write GPIF Data L & trigger transac.

Definition at line 214 of file fx2regs.h.

Defines

Variables

Detailed Description

Define Documentation

Variable Documentation