wafer.space Project Template | GitHub | Generated: 20 May 2026 12:07 UTC
| Slot | Die Size | Usable Silicon | Core Area | IO Overhead | Bidir | Inputs | Analog | Total IOs | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1×1 (Full) | 3.93 × 5.12mm (20.14mm²) |
3.88 × 5.07mm (19.67mm²) |
3.05 × 4.24mm (12.92mm²) |
36% | 40 | 14 | 2 | 56 | 8 | 10 | 18 | 74 |
| 0.5×1 (Half Width) | 1.94 × 5.12mm (9.92mm²) |
1.88 × 5.07mm (9.55mm²) |
1.05 × 4.24mm (4.46mm²) |
55% | 44 | 6 | 6 | 56 | 8 | 8 | 16 | 72 |
| 1×0.5 (Half Height) | 3.93 × 2.53mm (9.95mm²) |
3.88 × 2.48mm (9.62mm²) |
3.05 × 1.65mm (5.02mm²) |
50% | 46 | 6 | 4 | 56 | 8 | 8 | 16 | 72 |
| 0.5×0.5 (Quarter) | 1.94 × 2.53mm (4.90mm²) |
1.88 × 2.48mm (4.67mm²) |
1.05 × 1.65mm (1.73mm²) |
65% | 38 | 6 | 4 | 48 | 4 | 4 | 8 | 56 |
| 0.5×0.5 2-side EXACT (Quarter, no north/east; pads pinned to slot_1x1 coords) | 1.97 × 2.56mm (5.03mm²) |
1.91 × 2.51mm (4.80mm²) |
1.08 × 1.68mm (1.81mm²) |
64% | 4 | 8 | 2 | 14 | 1 | 1 | 2 | 16 |
| 0.5×1 3-side EXACT (Half Width, no east; pads pinned to slot_1x1 coords) | 1.97 × 5.12mm (10.07mm²) |
1.91 × 5.07mm (9.70mm²) |
1.08 × 4.24mm (4.59mm²) |
54% | 10 | 14 | 2 | 26 | 4 | 4 | 8 | 34 |
| 1×0.5 3-side EXACT (Half Height, no north; pads pinned to slot_1x1 coords) | 3.93 × 2.56mm (10.07mm²) |
3.88 × 2.51mm (9.73mm²) |
3.05 × 1.68mm (5.11mm²) |
49% | 20 | 8 | 2 | 30 | 2 | 3 | 5 | 35 |
Each slot has three important size measurements:
┌─────────────────────────────────────────┐
│ SEAL RING (26µm) │
│ ┌───────────────────────────────────┐ │
│ │ IO RING │ │
│ │ ┌─────────────────────────────┐ │ │
│ │ │ │ │ │
│ │ │ CORE AREA │ │ │
│ │ │ (Your Design Area) │ │ │
│ │ │ │ │ │
│ │ └─────────────────────────────┘ │ │
│ │ │ │
│ └───────────────────────────────────┘ │
│ │
└─────────────────────────────────────────┘
◄─────────── DIE SIZE ──────────────────►
◄────── USABLE SILICON ────────────►
◄────── CORE SIZE ───────────►
Half-sized variants of the 1×1 slot. One edge is a bare cut edge with no IO pads, so the padring covers only three sides.
| Slot | Die Size | Usable Silicon | Core Area | IO Overhead | Bidir | Inputs | Analog | Total IOs | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0.5×1 3-side (Half Width, no east) | 1.97 × 5.12mm (10.07mm²) |
1.91 × 5.07mm (9.70mm²) |
1.08 × 4.24mm (4.59mm²) |
54% | 14 | 14 | 2 | 30 | 4 | 6 | 10 | 40 |
| 1×0.5 3-side (Half Height, no south) | 3.93 × 2.56mm (10.07mm²) |
3.88 × 2.51mm (9.73mm²) |
3.05 × 1.68mm (5.11mm²) |
49% | 20 | 8 | 2 | 30 | 4 | 5 | 9 | 39 |
Each slot can be configured with different IO pad densities and edge arrangements to suit your design needs.
Choose how many IO pads you need:
Choose which edges have IO pads based on your slot position on the wafer:
Configurations are named using the pattern: {{slot}}_{{density}}_{{edges}}
Example: 0p5x0p5_max_all = 0.5×0.5 slot, maximum pads, all edges
Each slot size has multiple configuration variants. Click on a slot to expand its variants. Click on images to view full size.
| Diagram | Image | Config Name | Density | Edges | Core Area | Bidir | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|
1x1_def_all |
Default | All Edges | 3.05 × 4.24mm | 40 | 8 | 10 | 18 | 74 | ||
1x1_max_all |
Maximum | All Edges | 3.05 × 4.24mm | 168 | 15 | 15 | 30 | 200 | ||
1x1_max_top |
Maximum | Top Only | 3.05 × 4.24mm | 34 | 3 | 3 | 6 | 42 | ||
1x1_max_lft |
Maximum | Left Only | 3.05 × 4.24mm | 48 | 4 | 4 | 8 | 58 | ||
1x1_max_hor |
Maximum | Horizontal | 3.05 × 4.24mm | 70 | 6 | 6 | 12 | 84 | ||
1x1_max_ver |
Maximum | Vertical | 3.05 × 4.24mm | 96 | 9 | 9 | 18 | 116 | ||
1x1_max_nwc |
Maximum | NW Corner | 3.05 × 4.24mm | 84 | 7 | 7 | 14 | 100 | ||
1x1_max_sec |
Maximum | SE Corner | 3.05 × 4.24mm | 84 | 7 | 7 | 14 | 100 |
| Diagram | Image | Config Name | Density | Edges | Core Area | Bidir | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|
0p5x1_def_all |
Default | All Edges | 1.05 × 4.24mm | 44 | 8 | 8 | 16 | 72 | ||
0p5x1_max_all |
Maximum | All Edges | 1.05 × 4.24mm | 122 | 11 | 11 | 22 | 146 | ||
0p5x1_max_top |
Maximum | Top Only | 1.05 × 4.24mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x1_max_lft |
Maximum | Left Only | 1.05 × 4.24mm | 48 | 4 | 4 | 8 | 58 | ||
0p5x1_max_hor |
Maximum | Horizontal | 1.05 × 4.24mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x1_max_ver |
Maximum | Vertical | 1.05 × 4.24mm | 96 | 9 | 9 | 18 | 116 | ||
0p5x1_max_nwc |
Maximum | NW Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x1_max_sec |
Maximum | SE Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x1_spc_all |
1x1 Spacing | All Edges | 1.05 × 4.24mm | 122 | 11 | 11 | 22 | 146 | ||
0p5x1_spc_top |
1x1 Spacing | Top Only | 1.05 × 4.24mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x1_spc_lft |
1x1 Spacing | Left Only | 1.05 × 4.24mm | 48 | 4 | 4 | 8 | 58 | ||
0p5x1_spc_hor |
1x1 Spacing | Horizontal | 1.05 × 4.24mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x1_spc_ver |
1x1 Spacing | Vertical | 1.05 × 4.24mm | 96 | 9 | 9 | 18 | 116 | ||
0p5x1_spc_nwc |
1x1 Spacing | NW Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x1_spc_sec |
1x1 Spacing | SE Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x1_num_all |
1x1 Count | All Edges | 1.05 × 4.24mm | 62 | 5 | 5 | 10 | 74 | ||
0p5x1_num_top |
1x1 Count | Top Only | 1.05 × 4.24mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x1_num_lft |
1x1 Count | Left Only | 1.05 × 4.24mm | 48 | 4 | 4 | 8 | 58 | ||
0p5x1_num_hor |
1x1 Count | Horizontal | 1.05 × 4.24mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x1_num_ver |
1x1 Count | Vertical | 1.05 × 4.24mm | 62 | 5 | 5 | 10 | 74 | ||
0p5x1_num_nwc |
1x1 Count | NW Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x1_num_sec |
1x1 Count | SE Corner | 1.05 × 4.24mm | 61 | 5 | 5 | 10 | 73 |
| Diagram | Image | Config Name | Density | Edges | Core Area | Bidir | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|
1x0p5_def_all |
Default | All Edges | 3.05 × 1.65mm | 46 | 8 | 8 | 16 | 72 | ||
1x0p5_max_all |
Maximum | All Edges | 3.05 × 1.65mm | 108 | 10 | 10 | 20 | 130 | ||
1x0p5_max_top |
Maximum | Top Only | 3.05 × 1.65mm | 34 | 3 | 3 | 6 | 42 | ||
1x0p5_max_lft |
Maximum | Left Only | 3.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
1x0p5_max_hor |
Maximum | Horizontal | 3.05 × 1.65mm | 70 | 6 | 6 | 12 | 84 | ||
1x0p5_max_ver |
Maximum | Vertical | 3.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
1x0p5_max_nwc |
Maximum | NW Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 | ||
1x0p5_max_sec |
Maximum | SE Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 | ||
1x0p5_spc_all |
1x1 Spacing | All Edges | 3.05 × 1.65mm | 108 | 10 | 10 | 20 | 130 | ||
1x0p5_spc_top |
1x1 Spacing | Top Only | 3.05 × 1.65mm | 34 | 3 | 3 | 6 | 42 | ||
1x0p5_spc_lft |
1x1 Spacing | Left Only | 3.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
1x0p5_spc_hor |
1x1 Spacing | Horizontal | 3.05 × 1.65mm | 70 | 6 | 6 | 12 | 84 | ||
1x0p5_spc_ver |
1x1 Spacing | Vertical | 3.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
1x0p5_spc_nwc |
1x1 Spacing | NW Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 | ||
1x0p5_spc_sec |
1x1 Spacing | SE Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 | ||
1x0p5_num_all |
1x1 Count | All Edges | 3.05 × 1.65mm | 62 | 5 | 5 | 10 | 74 | ||
1x0p5_num_top |
1x1 Count | Top Only | 3.05 × 1.65mm | 34 | 3 | 3 | 6 | 42 | ||
1x0p5_num_lft |
1x1 Count | Left Only | 3.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
1x0p5_num_hor |
1x1 Count | Horizontal | 3.05 × 1.65mm | 62 | 5 | 5 | 10 | 74 | ||
1x0p5_num_ver |
1x1 Count | Vertical | 3.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
1x0p5_num_nwc |
1x1 Count | NW Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 | ||
1x0p5_num_sec |
1x1 Count | SE Corner | 3.05 × 1.65mm | 53 | 5 | 5 | 10 | 65 |
| Diagram | Image | Config Name | Density | Edges | Core Area | Bidir | DVDD | DVSS | Power Pads | Total Pads |
|---|---|---|---|---|---|---|---|---|---|---|
0p5x0p5_def_all |
Default | All Edges | 1.05 × 1.65mm | 38 | 4 | 4 | 8 | 56 | ||
0p5x0p5_max_all |
Maximum | All Edges | 1.05 × 1.65mm | 62 | 6 | 6 | 12 | 76 | ||
0p5x0p5_max_top |
Maximum | Top Only | 1.05 × 1.65mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x0p5_max_lft |
Maximum | Left Only | 1.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
0p5x0p5_max_hor |
Maximum | Horizontal | 1.05 × 1.65mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x0p5_max_ver |
Maximum | Vertical | 1.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
0p5x0p5_max_nwc |
Maximum | NW Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 | ||
| - | 0p5x0p5_max_sec |
Maximum | SE Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 | |
0p5x0p5_spc_all |
1x1 Spacing | All Edges | 1.05 × 1.65mm | 62 | 6 | 6 | 12 | 76 | ||
0p5x0p5_spc_top |
1x1 Spacing | Top Only | 1.05 × 1.65mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x0p5_spc_lft |
1x1 Spacing | Left Only | 1.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
0p5x0p5_spc_hor |
1x1 Spacing | Horizontal | 1.05 × 1.65mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x0p5_spc_ver |
1x1 Spacing | Vertical | 1.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
0p5x0p5_spc_nwc |
1x1 Spacing | NW Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 | ||
0p5x0p5_spc_sec |
1x1 Spacing | SE Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 | ||
0p5x0p5_num_all |
1x1 Count | All Edges | 1.05 × 1.65mm | 61 | 5 | 5 | 10 | 73 | ||
0p5x0p5_num_top |
1x1 Count | Top Only | 1.05 × 1.65mm | 11 | 1 | 1 | 2 | 15 | ||
0p5x0p5_num_lft |
1x1 Count | Left Only | 1.05 × 1.65mm | 17 | 2 | 2 | 4 | 23 | ||
0p5x0p5_num_hor |
1x1 Count | Horizontal | 1.05 × 1.65mm | 24 | 2 | 2 | 4 | 30 | ||
0p5x0p5_num_ver |
1x1 Count | Vertical | 1.05 × 1.65mm | 38 | 3 | 3 | 6 | 46 | ||
0p5x0p5_num_nwc |
1x1 Count | NW Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 | ||
0p5x0p5_num_sec |
1x1 Count | SE Corner | 1.05 × 1.65mm | 30 | 3 | 3 | 6 | 38 |
The *_3side_exact configs pin every retained
signal/power pad (via a custom PAD_CFG) to the
exact (x, y) it occupies in a real
slot_1x1 build. Below,
blue =
slot_1x1 pads,
red outline =
the exact 3-side pads. Every red box bounds its blue pad with a
verified 0.0 µm offset; blue-only pads
sit across the bare cut edge and are intentionally dropped.