GF180MCU Slot Sizes

Available Slots

1×1 (Full)

Die Size

3.93mm × 5.12mm (20.14mm²)

Usable Silicon

3.88mm × 5.07mm (19.67mm²)

Core Area

3.05mm × 4.24mm (12.92mm²)

IO Overhead

36%

Total IOs

56 (bidir: 40, in: 14, analog: 2)

Total Pads

72 (56 IO + 16 power)

0.5×1 (Half Width)

Die Size

1.94mm × 5.12mm (9.92mm²)

Usable Silicon

1.88mm × 5.07mm (9.55mm²)

Core Area

1.05mm × 4.24mm (4.46mm²)

IO Overhead

55%

Total IOs

56 (bidir: 44, in: 6, analog: 6)

Total Pads

72 (56 IO + 16 power)

1×0.5 (Half Height)

Die Size

3.93mm × 2.53mm (9.95mm²)

Usable Silicon

3.88mm × 2.48mm (9.62mm²)

Core Area

3.05mm × 1.65mm (5.02mm²)

IO Overhead

50%

Total IOs

56 (bidir: 46, in: 6, analog: 4)

Total Pads

72 (56 IO + 16 power)

0.5×0.5 (Quarter)

Die Size

1.94mm × 2.53mm (4.90mm²)

Usable Silicon

1.88mm × 2.48mm (4.67mm²)

Core Area

1.05mm × 1.65mm (1.73mm²)

IO Overhead

65%

Total IOs

48 (bidir: 38, in: 6, analog: 4)

Total Pads

56 (48 IO + 8 power)

Detailed Specifications

Understanding Slot Dimensions

Each slot has three important size measurements:

┌─────────────────────────────────────────┐
│             SEAL RING (26µm)            │
│  ┌───────────────────────────────────┐  │
│  │           IO RING                 │  │
│  │  ┌─────────────────────────────┐  │  │
│  │  │                             │  │  │
│  │  │        CORE AREA            │  │  │
│  │  │    (Your Design Area)       │  │  │
│  │  │                             │  │  │
│  │  └─────────────────────────────┘  │  │
│  │                                   │  │
│  └───────────────────────────────────┘  │
│                                         │
└─────────────────────────────────────────┘
 ◄─────────── DIE SIZE ──────────────────►
   ◄────── USABLE SILICON ────────────►
      ◄────── CORE SIZE ───────────►
                

Die Size

The actual physical silicon dimensions. This is the total area of the chip including all peripheral structures.

Usable Silicon

The die size minus the seal ring (26µm on each edge). The seal ring protects the chip from damage during dicing and provides a moisture barrier. This is the area available inside the seal ring.

Core Area

The usable design area inside the IO ring. This is where your digital logic, analog circuits, and other design elements are placed. The IO ring contains the pad cells that connect your design to the outside world.

IO Configuration Options

Each slot can be configured with different IO pad densities and edge arrangements to suit your design needs.

Pad Density Modes

Choose how many IO pads you need:

Default (def)

Standard configuration with mixed pad types: bidirectional, input-only, and analog pads. Best for typical designs that need different pad characteristics.

Maximum (max)

Maximum number of pads possible for the slot size. All signal pads are bidirectional for maximum flexibility.

1x1 Spacing (spc)

Same pad spacing as the full 1x1 slot. Useful for maintaining consistent pad pitch across different slot sizes.

1x1 Count (num)

Same total pad count as the reference 1x1 slot. Ensures IO count compatibility when migrating designs.

Edge Configurations

Choose which edges have IO pads based on your slot position on the wafer:

All Edges (all)

IO pads on all four sides. Standard configuration for standalone designs.

Top Only (top)

IO pads only on the north edge. Ideal for slots positioned at the bottom of a multi-slot arrangement.

Left Only (lft)

IO pads only on the west edge. Ideal for slots positioned on the right side.

Horizontal (hor)

IO pads on north and south edges only. For slots that will connect to neighbors on left and right.

Vertical (ver)

IO pads on east and west edges only. For slots that will connect to neighbors above and below.

NW Corner (nwc)

IO pads on north and west edges. For slots positioned in the southeast corner of an arrangement.

SE Corner (sec)

IO pads on south and east edges. For slots positioned in the northwest corner of an arrangement.

Configuration Naming

Configurations are named using the pattern: {{slot}}_{{density}}_{{edges}}

Example: 0p5x0p5_max_all = 0.5×0.5 slot, maximum pads, all edges

Configuration Variants

Each slot size has multiple configuration variants. Click on a slot to expand its variants. Click on images to view full size.