Fx2lib  0.2
include/eputils.h
Go to the documentation of this file.
00001 // Copyright (C) 2009 Ubixum, Inc. 
00002 // 
00003 // This library is free software; you can redistribute it and/or
00004 // modify it under the terms of the GNU Lesser General Public
00005 // License as published by the Free Software Foundation; either
00006 // version 2.1 of the License, or (at your option) any later version.
00007 // 
00008 // This library is distributed in the hope that it will be useful,
00009 // but WITHOUT ANY WARRANTY; without even the implied warranty of
00010 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00011 // Lesser General Public License for more details.
00012 // 
00013 // You should have received a copy of the GNU Lesser General Public
00014 // License along with this library; if not, write to the Free Software
00015 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
00016 
00021 #ifndef EPUTILS_H
00022 #define EPUTILS_H
00023 
00024 #include <assert.h>
00025 
00026 #include "fx2types.h"
00027 #include "fx2macros.h"
00028 
00047 #define STALLEP0() EP0CS |= bmEPSTALL
00048 
00053 #define RESETTOGGLE(ep) do {\
00054         BYTE x = ep; \
00055         if (x&0x80) { x |= 0x10; } \
00056         x &= 0x1F; \
00057         TOGCTL = x; \
00058         TOGCTL = x | bmRESETTOGGLE; \
00059 } while (0)
00060 
00061 
00066 #define RESETFIFO(ep) {FIFORESET=0x80; SYNCDELAY;\
00067                        FIFORESET=0x80 | ep; SYNCDELAY;\
00068                        FIFORESET=0x00; SYNCDELAY;}
00069 
00072 #define RESETFIFOS() {FIFORESET=0x80; SYNCDELAY;\
00073                      FIFORESET=0x82; SYNCDELAY;\
00074                      FIFORESET=0x84; SYNCDELAY;\
00075                      FIFORESET=0x86; SYNCDELAY;\
00076                      FIFORESET=0x88; SYNCDELAY;\
00077                      FIFORESET=0x00; SYNCDELAY;}
00078 
00084 void readep0( BYTE* dst, WORD len );
00085 
00090 void writeep0( BYTE* src, WORD len );
00091 
00092 // The Setup Data Pointer can access data in either of two RAM spaces:
00093 //  - On-chip Main RAM (8 KB at 0x0000-0x1FFF)
00094 //  - On-chip Scratch RAM (512 bytes at 0xE000-0xE1FF)
00095 // The base address of SUDPTRH:L must be word-aligned.
00096 #define ep0_load_sudptr(src) \
00097         assert( \
00098                 (((WORD)src) <= 0x3FFF) || \
00099                 (((WORD)src) >= 0xE000 && ((WORD)src) <= 0xE1FF)); \
00100         assert(!(LSB(src) & bmBIT0)); \
00101         LOADWORD(SUDPTR, src);
00102 
00103 // For manual mode, SUDPTRCTL must be in "auto read length mode".
00104 //
00105 // |  Data Read  | Data Length | SUDPTRCTL |
00106 // |-------------|-------------|-----------|
00107 // | Auto   (0)  | Manual (0)  |  0|0 = 0  | SUDPTR->EP0BC
00108 // | Manual (1)  | Manual (0)  |  1|0 = 1  | EP0BUF->EP0BC
00109 // | Auto   (0)  | Auto   (1)  |  0|1 = 1  | SUDPTR
00110 // | Manual (1)  | Auto   (1)  |  Invalid  | NA
00111 enum ep0_mode_data {
00112         EP0_DATA_AUTO    = 0,
00113         EP0_DATA_MANUAL  = 1,
00114 };
00115 enum ep0_mode_length {
00116         EP0_LENGTH_AUTO   = 1,
00117         EP0_LENGTH_MANUAL = 0,
00118 };
00119 
00120 #define ep0_mode(mode_data, mode_length) \
00121         assert(!(mode_data & mode_length)); \
00122         SUDPTRCTL = mode_data | mode_length;
00123 
00124 #define ep0_busywait() \
00125         while (EP0CS & bmEPBUSY) printf("w\n");
00126 
00127 #define ep0_load_length(len) \
00128         LOADWORD(EP0BC, len);
00129 
00130 #define ep0_arm() \
00131         ep0_load_length(0);
00132 
00133 // ep0 can only receive 64 bytes
00134 #define ep0_get_length() \
00135         EP0BCL
00136 
00137 void ep0_send_auto(__xdata BYTE* src, WORD len);
00138 void ep0_send_byte(BYTE data);
00139 void ep0_send_word(WORD data);
00140 
00141 BYTE ep0_recv();
00142 
00143 #endif